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    Searched refs:cfgcr2 (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.h 190 u32 cfgcr1, cfgcr2; member in struct:intel_dpll_hw_state
intel_dpll_mgr.c 963 i915_reg_t ctl, cfgcr1, cfgcr2; member in struct:skl_dpll_regs
977 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
983 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
989 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
1019 I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
1021 POSTING_READ(regs[id].cfgcr2);
1081 hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2);
1372 u32 ctrl1, cfgcr1, cfgcr2; local
    [all...]
intel_ddi.c 1326 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1327 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1329 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1330 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
intel_display.c 13675 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);

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