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    Searched refs:chunk_hdl_adjust_cur0 (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
amdgpu_display_rq_dlg_helpers.c 306 "DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x%0x\n",
307 dlg_regs.chunk_hdl_adjust_cur0);
display_mode_structs.h 454 unsigned int chunk_hdl_adjust_cur0; member in struct:_vcs_dpi_display_dlg_regs_st
amdgpu_dml1_display_rq_dlg_calc.c 1728 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer_debug.c 279 dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
amdgpu_dcn10_hw_sequencer.c 246 dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_rq_dlg_calc_20.c 1513 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
amdgpu_display_rq_dlg_calc_20v2.c 1514 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_rq_dlg_calc_21.c 1613 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;

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