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  /src/sys/arch/arm/amlogic/
meson_sdhc.c 391 uint32_t clk2; local in function:meson_sdhc_set_clock
426 clk2 = SDHC_READ(sc, SD_CLK2_REG);
427 clk2 &= ~SD_CLK2_SD_CLK_PHASE;
428 clk2 |= __SHIFTIN(1, SD_CLK2_SD_CLK_PHASE);
429 clk2 &= ~SD_CLK2_RX_CLK_PHASE;
430 clk2 |= __SHIFTIN(meson_sdhc_default_rx_phase(sc),
432 SDHC_WRITE(sc, SD_CLK2_REG, clk2);
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
tegra30-apalis-v1.1.dtsi 152 clk2-out-pw5 {
446 clk2-req-pcc5 {
tegra30-apalis.dtsi 151 clk2-out-pw5 {
445 clk2-req-pcc5 {
tegra30-colibri.dtsi 250 clk2-out-pw5 {
611 clk2-req-pcc5 {
tegra124-apalis-v1.2.dtsi 330 clk2-out-pw5 { /* D5 GPIO */
379 clk2-req-pcc5 { /* D4 GPIO */
tegra124-apalis.dtsi 327 clk2-out-pw5 { /* D5 GPIO */
376 clk2-req-pcc5 { /* D4 GPIO */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/nvidia/
tegra210.dtsi 926 pins = "pex-bias", "pex-clk1", "pex-clk2";
933 pins = "pex-bias", "pex-clk1", "pex-clk2";
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/
msm8916.dtsi 1400 "mi2s-bit-clk2",

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