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    Searched refs:clk_mgr (Results 1 - 25 of 41) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
rn_clk_mgr_vbios_smu.h 31 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
32 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
33 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
34 int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
35 int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
36 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
37 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
38 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);
39 void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
40 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
    [all...]
amdgpu_rn_clk_mgr_vbios_smu.c 61 int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
78 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
81 clk_mgr,
87 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
90 struct dc *dc = clk_mgr->base.ctx->dc;
95 clk_mgr,
101 if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
110 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
115 clk_mgr,
117 clk_mgr->base.dprefclk_khz / 1000)
    [all...]
rn_clk_mgr.h 31 #include "clk_mgr.h"
39 struct clk_mgr_internal *clk_mgr,
amdgpu_rn_clk_mgr.c 101 void rn_update_clocks(struct clk_mgr *clk_mgr_base,
105 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rn_update_clocks
129 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
137 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);
145 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
150 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
156 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
165 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
166 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
174 rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz)
234 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rn_dump_clk_registers_internal
399 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rn_enable_pme_wa
474 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rn_notify_wm_ranges
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/
dce112_clk_mgr.h 34 struct clk_mgr_internal *clk_mgr);
37 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
38 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz);
39 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr);
amdgpu_dce112_clk_mgr.c 75 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
130 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
133 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
134 struct dc *dc = clk_mgr->base.ctx->dc;
143 clk_mgr->base.dentist_vco_freq_khz / 62);
157 clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
162 if (clk_mgr->dfs_bypass_disp_clk != actual_clock)
168 clk_mgr->dfs_bypass_disp_clk = actual_clock;
173 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr)
176 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
dcn20_clk_mgr.h 31 void dcn2_update_clocks(struct clk_mgr *dccg,
35 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
38 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
41 void dcn2_init_clocks(struct clk_mgr *clk_mgr);
44 struct clk_mgr_internal *clk_mgr,
50 void dcn2_get_clock(struct clk_mgr *clk_mgr,
55 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr);
    [all...]
amdgpu_dcn20_clk_mgr.c 48 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
51 (clk_mgr->regs->reg)
108 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
113 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
114 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
123 prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
126 clk_mgr->dccg->funcs->update_dpp_dto(
127 clk_mgr->dccg, dpp_inst, dppclk_khz)
155 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:dcn2_update_clocks
344 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:dcn2_enable_pme_wa
358 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:dcn2_read_clocks_from_hw_dentist
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
rv1_clk_mgr_vbios_smu.h 31 int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
32 int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
rv1_clk_mgr.h 31 void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
rv2_clk_mgr.h 31 void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
amdgpu_rv2_clk_mgr.c 42 void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu)
45 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);
47 clk_mgr->funcs = &rv2_clk_internal_funcs;
amdgpu_rv1_clk_mgr.c 42 void rv1_init_clocks(struct clk_mgr *clk_mgr)
44 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
47 static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
50 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz;
52 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz;
82 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold)
93 static void ramp_up_dispclk_with_dpp(struct clk_mgr_internal *clk_mgr, struct dc *dc, struct dc_clocks *new_clocks)
96 int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks)
134 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rv1_update_clocks
236 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rv1_enable_pme_wa
    [all...]
amdgpu_rv1_clk_mgr_vbios_smu.c 76 int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
93 int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
96 struct dc *dc = clk_mgr->base.ctx->dc;
101 clk_mgr,
110 if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
119 int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
124 clk_mgr,
126 clk_mgr->base.dprefclk_khz / 1000);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/
dce_clk_mgr.h 36 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
38 struct clk_mgr *clk_mgr_base,
50 int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);
53 struct clk_mgr *clk_mgr_base,
57 void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr);
amdgpu_dce_clk_mgr.c 52 (clk_mgr->regs->reg)
56 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
134 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
136 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:dce_get_dp_ref_freq_khz
155 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
157 return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
160 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
200 struct clk_mgr *clk_mgr_base,
235 struct clk_mgr *clk_mgr_base
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/
dce120_clk_mgr.h 31 void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr);
32 void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr);
amdgpu_dce120_clk_mgr.c 89 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base,
133 void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr)
135 dce_clk_mgr_construct(ctx, clk_mgr);
137 memcpy(clk_mgr->max_clks_by_state,
141 clk_mgr->base.dprefclk_khz = 600000;
142 clk_mgr->base.funcs = &dce120_funcs;
145 void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr)
147 dce120_clk_mgr_construct(ctx, clk_mgr);
148 clk_mgr->base.dprefclk_khz = 625000;
155 dce121_clock_patch_xgmi_ss_info(clk_mgr);
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/
amdgpu_clk_mgr.c 71 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
79 clk_mgr->psr_allow_active_cache = edp_link->psr_allow_active;
85 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
90 dc_link_set_psr_allow_active(edp_link, clk_mgr->psr_allow_active_cache, false);
97 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
101 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); local in function:dc_clk_mgr_create
103 if (clk_mgr == NULL)
179 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:dc_destroy_clk_mgr
    [all...]
Makefile 23 # Makefile for the 'clk_mgr' sub-component of DAL.
24 # It provides the control and status of HW CLK_MGR pins.
26 CLK_MGR = clk_mgr.o
28 AMD_DAL_CLK_MGR = $(addprefix $(AMDDALPATH)/dc/clk_mgr/,$(CLK_MGR))
38 AMD_DAL_CLK_MGR_DCE100 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce100/,$(CLK_MGR_DCE100))
47 AMD_DAL_CLK_MGR_DCE110 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce110/,$(CLK_MGR_DCE110))
55 AMD_DAL_CLK_MGR_DCE112 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce112/,$(CLK_MGR_DCE112))
63 AMD_DAL_CLK_MGR_DCE120 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce120/,$(CLK_MGR_DCE120)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
clk_mgr.h 1 /* $NetBSD: clk_mgr.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */
170 void (*update_clocks)(struct clk_mgr *clk_mgr,
174 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);
176 void (*init_clocks)(struct clk_mgr *clk_mgr);
178 void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
179 void (*get_clock)(struct clk_mgr *clk_mgr
189 struct clk_mgr { struct
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_clk_mgr.c 53 clk_mgr->ctx->logger
153 static int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr)
155 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
179 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr)
181 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
219 struct clk_mgr *clk_mgr,
222 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
dce110_clk_mgr.h 33 struct clk_mgr_internal *clk_mgr);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/
amdgpu_dce100_hw_sequencer.c 33 #include "clk_mgr.h"
119 dc->clk_mgr->funcs->update_clocks(
120 dc->clk_mgr,
131 dc->clk_mgr->funcs->update_clocks(
132 dc->clk_mgr,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hwseq.c 39 #include "hw/clk_mgr.h"
104 dc->clk_mgr->funcs->update_clocks(
105 dc->clk_mgr,
114 dc->clk_mgr->funcs->update_clocks(
115 dc->clk_mgr,

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