| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/ |
| amdgpu_dce_clk_mgr.c | 119 int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz)
121 if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) {
123 dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage,
124 clk_mgr_dce->dprefclk_ss_divider), 200);
162 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); local
164 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz);
203 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); local
212 for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
214 clk_mgr_dce->max_clks_by_state[i].display_clk_kh
238 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); local
404 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); local
[all...] |
| dce_clk_mgr.h | 35 int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz);
46 struct clk_mgr_internal *clk_mgr_dce);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_clk_mgr.c | 44 (clk_mgr_dce->regs->reg)
48 clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name
51 clk_mgr_dce->base.ctx
138 static int clk_mgr_adjust_dp_ref_freq_for_ss(struct dce_clk_mgr *clk_mgr_dce, int dp_ref_clk_khz)
140 if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) {
142 dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage,
143 clk_mgr_dce->dprefclk_ss_divider), 200);
155 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr) local
181 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); local
222 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); local
255 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); local
295 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); local
471 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); local
677 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); local
704 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); local
731 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); local
758 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); local
852 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); local
875 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); local
900 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); local
921 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); local
943 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), local
964 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(*clk_mgr); local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/ |
| amdgpu_dce120_clk_mgr.c | 54 * @clk_mgr_dce: clock manager internal structure
61 static void dce121_clock_patch_xgmi_ss_info(struct clk_mgr_internal *clk_mgr_dce)
65 struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
67 clk_mgr_dce->xgmi_enabled = false;
72 clk_mgr_dce->xgmi_enabled = true;
73 clk_mgr_dce->ss_on_dprefclk = true;
74 clk_mgr_dce->dprefclk_ss_divider =
83 clk_mgr_dce->dprefclk_ss_percentage =
93 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); local
99 if (!clk_mgr_dce->dfs_bypass_active
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/ |
| amdgpu_dce112_clk_mgr.c | 77 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); local
89 clk_mgr_dce->base.dentist_vco_freq_khz / 62);
103 clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
120 if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
126 clk_mgr_dce->dfs_bypass_disp_clk = actual_clock;
202 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); local
207 if (!clk_mgr_dce->dfs_bypass_active)
212 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
213 || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
215 clk_mgr_dce->cur_min_clks_state = level_change_req.power_level
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 257 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); local
262 if (!clk_mgr_dce->dfs_bypass_active)
267 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
268 || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
270 clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
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