| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega10_processpptables.c | 580 phm_ppt_v1_clock_voltage_dependency_table *clk_table; local in function:get_socclk_voltage_dependency_table
589 clk_table = kzalloc(table_size, GFP_KERNEL);
591 if (!clk_table)
594 clk_table->count = (uint32_t)clk_dep_table->ucNumEntries;
597 clk_table->entries[i].vddInd =
599 clk_table->entries[i].clk =
603 *pp_vega10_clk_dep_table = clk_table;
654 *clk_table; local in function:get_gfxclk_voltage_dependency_table
664 clk_table = kzalloc(table_size, GFP_KERNEL);
666 if (!clk_table)
721 *clk_table; local in function:get_pix_clk_voltage_dependency_table
758 *clk_table; local in function:get_dcefclk_voltage_dependency_table
[all...] |
| amdgpu_process_pptables_v1_0.c | 322 struct phm_clock_array **clk_table,
349 *clk_table = table;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_renoir_ppt.c | 233 DpmClocks_t *clk_table = smu->smu_table.clocks_table; local in function:renoir_get_dpm_clk_limited
235 if (!clk_table || clk_type >= SMU_CLK_COUNT)
238 GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
248 DpmClocks_t *clk_table = smu->smu_table.clocks_table; local in function:renoir_print_clk_levels
251 if (!clk_table || clk_type >= SMU_CLK_COUNT)
305 GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
614 DpmClocks_t *clk_table = smu->smu_table.clocks_table; local in function:renoir_force_clk_levels
642 GET_DPM_CUR_FREQ(clk_table, clk_type, soft_min_level, min_freq);
643 GET_DPM_CUR_FREQ(clk_table, clk_type, soft_max_level, max_freq);
653 GET_DPM_CUR_FREQ(clk_table, clk_type, soft_min_level, min_freq)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| amdgpu_rn_clk_mgr.c | 436 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
438 ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
515 .clk_table = {
663 bw_params->clk_table.num_entries = j + 1;
665 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
666 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
667 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
668 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
669 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
678 if (i >= bw_params->clk_table.num_entries)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| clk_mgr.h | 153 struct clk_limit_table clk_table; member in struct:clk_bw_params
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 1099 vlevel_max = bw_params->clk_table.num_entries - 1;
1342 struct clk_limit_table *clk_table = &bw_params->clk_table; local in function:update_bw_bounding_box
1349 for (i = 0; i < clk_table->num_entries; i++) {
1352 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1353 dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1354 dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1355 dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
|
