| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| renoir_ppt.h | 35 #define GET_DPM_CUR_FREQ(table, clk_type, dpm_level, freq) \
37 switch (clk_type) { \
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| amdgpu_smu_v12_0.c | 379 int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
393 switch (clk_type) {
408 ret = smu_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
413 ret = smu_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
424 switch (clk_type) {
439 ret = smu_get_dpm_clk_limited(smu, clk_type, 0, min);
444 ret = smu_get_dpm_clk_limited(smu, clk_type, 0, min);
461 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
469 switch (clk_type) {
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| amdgpu_renoir_ppt.c | 230 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
235 if (!clk_table || clk_type >= SMU_CLK_COUNT)
238 GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
244 enum smu_clk_type clk_type, char *buf)
251 if (!clk_table || clk_type >= SMU_CLK_COUNT)
260 switch (clk_type) {
305 GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
395 enum smu_clk_type clk_type,
405 clk_id = smu_clk_get_index(smu, clk_type);
418 enum smu_clk_type clk_type; local in function:renoir_force_dpm_limit_value
445 enum smu_clk_type clk_type; local in function:renoir_unforce_dpm_levels
448 enum smu_clk_type clk_type; member in struct:renoir_unforce_dpm_levels::clk_feature_map
[all...] |
| smu_internal.h | 184 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
185 ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
200 #define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
201 ((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
203 #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
204 ((smu)->ppt_funcs->set_soft_freq_limited_range ? (smu)->ppt_funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
|
| amdgpu_navi10_ppt.c | 716 enum smu_clk_type clk_type,
726 clk_id = smu_clk_get_index(smu, clk_type);
735 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
741 clk_index = smu_clk_get_index(smu, clk_type);
764 enum smu_clk_type clk_type, char *buf)
782 switch (clk_type) {
790 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
797 ret = smu_get_dpm_level_count(smu, clk_type, &count);
801 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
803 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value)
1099 enum smu_clk_type clk_type; local in function:navi10_force_dpm_limit_value
1126 enum smu_clk_type clk_type; local in function:navi10_unforce_dpm_levels
[all...] |
| amdgpu_smu.c | 227 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
235 if (!smu_clk_dpm_is_enabled(smu, clk_type))
238 ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
242 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
251 if (!smu_clk_dpm_is_enabled(smu, clk_type))
254 clk_id = smu_clk_get_index(smu, clk_type);
278 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
290 if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
291 switch (clk_type) {
318 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max)
[all...] |
| amdgpu_smu_v11_0.c | 1319 enum amd_pp_clock_type clk_type = clock_req->clock_type; local in function:smu_v11_0_display_clock_voltage_request
1329 switch (clk_type) {
1769 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1775 clk_id = smu_clk_get_index(smu, clk_type);
1804 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
1810 clk_id = smu_clk_get_index(smu, clk_type);
|
| amdgpu_vega20_ppt.c | 1282 enum smu_clk_type clk_type, uint32_t mask)
1294 switch (clk_type) {
1445 enum smu_clk_type clk_type,
1455 switch (clk_type) {
1737 enum smu_clk_type clk_type)
1749 switch (clk_type) {
2527 enum smu_clk_type clk_type,
2543 switch (clk_type) {
|
| amdgpu_arcturus_ppt.c | 1068 enum smu_clk_type clk_type,
1077 clk_id = smu_clk_get_index(smu, clk_type);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services_types.h | 84 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
85 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
86 (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
87 (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
88 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
89 (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
90 (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
91 (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
92 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \
93 (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" :
256 enum dm_pp_clock_type clk_type; member in struct:dm_pp_clock_for_voltage_req
[all...] |
| dm_services.h | 204 * input: clk_type - display clk / sclk / mem clk
212 enum dm_pp_clock_type clk_type,
217 enum dm_pp_clock_type clk_type,
222 enum dm_pp_clock_type clk_type,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| smu_v12_0.h | 87 int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
92 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
|
| amdgpu_smu.h | 430 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
431 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
433 int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type);
435 enum smu_clk_type clk_type,
441 enum smu_clk_type clk_type,
477 enum smu_clk_type clk_type,
486 int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type,
567 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
568 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
593 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
[all...] |
| smu_v11_0.h | 257 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
260 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_pp_smu.c | 125 enum dm_pp_clock_type clk_type,
134 switch (clk_type) {
338 enum dm_pp_clock_type clk_type,
349 dc_to_pp_clock_type(clk_type), &pp_clks)) {
351 get_default_clock_levels(clk_type, dc_clks);
356 dc_to_pp_clock_type(clk_type),
358 get_default_clock_levels(clk_type, dc_clks);
363 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
396 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
408 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/ |
| amdgpu_dce120_clk_mgr.c | 103 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
118 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| atombios_crtc.h | 43 u32 freq, u8 clk_type, u8 clk_src);
|
| amdgpu_atombios_crtc.c | 533 u32 freq, u8 clk_type, u8 clk_src)
552 args.v2_1.asParam.ucDCEClkType = clk_type;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_clk_mgr.c | 768 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
783 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_smu10_hwmgr.c | 67 enum amd_pp_clock_type clk_type = clock_req->clock_type; local in function:smu10_display_clock_voltage_request
71 switch (clk_type) {
|
| amdgpu_vega12_hwmgr.c | 1440 enum amd_pp_clock_type clk_type = clock_req->clock_type; local in function:vega12_display_clock_voltage_request
1446 switch (clk_type) {
|
| amdgpu_vega20_hwmgr.c | 2256 enum amd_pp_clock_type clk_type = clock_req->clock_type; local in function:vega20_display_clock_voltage_request
2262 switch (clk_type) {
|
| amdgpu_vega10_hwmgr.c | 3910 enum amd_pp_clock_type clk_type = clock_req->clock_type; local in function:vega10_display_clock_voltage_request
3915 switch (clk_type) {
|
