| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| zynq-7000.dtsi | 19 clocks = <&clkc 3>;
33 clocks = <&clkc 3>;
64 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
107 clocks = <&clkc 12>;
113 clocks = <&clkc 19>, <&clkc 36>;
125 clocks = <&clkc 20>, <&clkc 37>
302 clkc: clkc@100 { label in label:amba.slcr
[all...] |
| meson8b.dtsi | 7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
27 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
29 clocks = <&clkc CLKID_CPUCLK>;
39 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
41 clocks = <&clkc CLKID_CPUCLK>;
51 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
53 clocks = <&clkc CLKID_CPUCLK>;
63 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>
589 clkc: clock-controller { label
[all...] |
| meson8.dtsi | 6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
29 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
31 clocks = <&clkc CLKID_CPUCLK>;
41 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
43 clocks = <&clkc CLKID_CPUCLK>;
53 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
55 clocks = <&clkc CLKID_CPUCLK>;
65 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>
611 clkc: clock-controller { label
[all...] |
| meson8m2.dtsi | 13 &clkc {
14 compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
31 clocks = <&clkc CLKID_ETH>,
32 <&clkc CLKID_MPLL2>,
33 <&clkc CLKID_MPLL2>,
34 <&clkc CLKID_FCLK_DIV2>;
79 assigned-clocks = <&clkc CLKID_VPU>;
|
| zynq-zed.dts | 35 &clkc {
|
| zynq-zybo-z7.dts | 41 &clkc {
|
| zynq-zybo.dts | 36 &clkc {
|
| zynq-ebaz4205.dts | 27 &clkc {
38 assigned-clocks = <&clkc 18>;
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/ |
| meson-gxbb.dtsi | 10 #include <dt-bindings/clock/gxbb-clkc.h>
23 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
33 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
42 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
54 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
66 clocks = <&clkc CLKID_AIU_GLUE>,
67 <&clkc CLKID_I2S_OUT>,
68 <&clkc CLKID_AOCLK_GATE>
321 clkc: clock-controller { label
[all...] |
| meson-gxl.dtsi | 8 #include <dt-bindings/clock/gxbb-clkc.h>
25 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
38 clocks = <&clkc CLKID_USB1>;
62 clocks = <&clkc CLKID_ACODEC>;
73 clocks = <&clkc CLKID_BLKMV>;
82 clocks = <&clkc CLKID_AIU_GLUE>,
83 <&clkc CLKID_I2S_OUT>,
84 <&clkc CLKID_AOCLK_GATE>,
85 <&clkc CLKID_CTS_AMCLK>
333 clkc: clock-controller { label
[all...] |
| meson-g12b-khadas-vim3.dtsi | 53 clocks = <&clkc CLKID_CPU_CLK>;
60 clocks = <&clkc CLKID_CPU_CLK>;
67 clocks = <&clkc CLKID_CPUB_CLK>;
74 clocks = <&clkc CLKID_CPUB_CLK>;
81 clocks = <&clkc CLKID_CPUB_CLK>;
88 clocks = <&clkc CLKID_CPUB_CLK>;
|
| meson-axg.dtsi | 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h>
117 clocks = <&clkc CLKID_EFUSE>;
191 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
217 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
235 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>
1217 clkc: clock-controller { label in label:hiubus.sysctrl
[all...] |
| meson-g12-common.dtsi | 8 #include <dt-bindings/clock/g12a-clkc.h>
35 clocks = <&clkc CLKID_HDMI>,
36 <&clkc CLKID_HTX_PCLK>,
37 <&clkc CLKID_VPU_INTR>;
45 clocks = <&clkc CLKID_HDMI>,
46 <&clkc CLKID_HTX_PCLK>,
47 <&clkc CLKID_VPU_INTR>;
54 clocks = <&clkc CLKID_EFUSE>;
146 clocks = <&clkc CLKID_PCIE_PHY
147 &clkc CLKID_PCIE_COM
1640 clkc: clock-controller { label in label:hiu.hhi
[all...] |
| meson-sm1-khadas-vim3l.dts | 53 clocks = <&clkc CLKID_CPU_CLK>;
60 clocks = <&clkc CLKID_CPU1_CLK>;
67 clocks = <&clkc CLKID_CPU2_CLK>;
74 clocks = <&clkc CLKID_CPU3_CLK>;
|
| meson-g12b-gsking-x.dts | 45 assigned-clocks = <&clkc CLKID_MPLL2>,
46 <&clkc CLKID_MPLL0>,
47 <&clkc CLKID_MPLL1>;
|
| meson-g12b-gtking-pro.dts | 54 assigned-clocks = <&clkc CLKID_MPLL2>,
55 <&clkc CLKID_MPLL0>,
56 <&clkc CLKID_MPLL1>;
|
| meson-gxbb-wetek-play2.dts | 54 assigned-clocks = <&clkc CLKID_MPLL0>,
55 <&clkc CLKID_MPLL1>,
56 <&clkc CLKID_MPLL2>;
|
| meson-g12.dtsi | 8 #include <dt-bindings/clock/axg-audio-clkc.h>
72 compatible = "amlogic,g12a-audio-clkc";
77 clocks = <&clkc CLKID_AUDIO>,
78 <&clkc CLKID_MPLL0>,
79 <&clkc CLKID_MPLL1>,
80 <&clkc CLKID_MPLL2>,
81 <&clkc CLKID_MPLL3>,
82 <&clkc CLKID_HIFI_PLL>,
83 <&clkc CLKID_FCLK_DIV3>,
84 <&clkc CLKID_FCLK_DIV4>
[all...] |
| meson-sm1.dtsi | 8 #include <dt-bindings/clock/axg-audio-clkc.h>
170 compatible = "amlogic,sm1-audio-clkc";
175 clocks = <&clkc CLKID_AUDIO>,
176 <&clkc CLKID_MPLL0>,
177 <&clkc CLKID_MPLL1>,
178 <&clkc CLKID_MPLL2>,
179 <&clkc CLKID_MPLL3>,
180 <&clkc CLKID_HIFI_PLL>,
181 <&clkc CLKID_FCLK_DIV3>,
182 <&clkc CLKID_FCLK_DIV4>
[all...] |
| meson-g12b-gtking.dts | 41 assigned-clocks = <&clkc CLKID_MPLL2>,
42 <&clkc CLKID_MPLL0>,
43 <&clkc CLKID_MPLL1>;
|
| meson-g12b-ugoos-am6.dts | 36 assigned-clocks = <&clkc CLKID_MPLL2>,
37 <&clkc CLKID_MPLL0>,
38 <&clkc CLKID_MPLL1>;
|
| meson-g12b.dtsi | 112 &clkc {
113 compatible = "amlogic,g12b-clkc";
|
| meson-g12a-x96-max.dts | 163 assigned-clocks = <&clkc CLKID_MPLL2>,
164 <&clkc CLKID_MPLL0>,
165 <&clkc CLKID_MPLL1>;
264 clocks = <&clkc CLKID_CPU_CLK>;
271 clocks = <&clkc CLKID_CPU_CLK>;
278 clocks = <&clkc CLKID_CPU_CLK>;
285 clocks = <&clkc CLKID_CPU_CLK>;
|
| meson-sm1-odroid.dtsi | 177 assigned-clocks = <&clkc CLKID_MPLL2>,
178 <&clkc CLKID_MPLL0>,
179 <&clkc CLKID_MPLL1>;
235 clocks = <&clkc CLKID_CPU_CLK>;
242 clocks = <&clkc CLKID_CPU1_CLK>;
249 clocks = <&clkc CLKID_CPU2_CLK>;
256 clocks = <&clkc CLKID_CPU3_CLK>;
|
| /src/sys/arch/arm/amlogic/ |
| meson_sdhc.c | 364 const u_int clkc = SDHC_READ(sc, SD_CLKC_REG); local in function:meson_sdhc_default_rx_phase
365 const u_int clk_div = __SHIFTOUT(clkc, SD_CLKC_CLK_DIV);
390 uint32_t clkc; local in function:meson_sdhc_set_clock
394 clkc = SDHC_READ(sc, SD_CLKC_REG);
395 clkc &= ~SD_CLKC_TX_CLK_ENABLE;
396 clkc &= ~SD_CLKC_RX_CLK_ENABLE;
397 clkc &= ~SD_CLKC_SD_CLK_ENABLE;
398 SDHC_WRITE(sc, SD_CLKC_REG, clkc);
399 clkc &= ~SD_CLKC_MOD_CLK_ENABLE;
400 SDHC_WRITE(sc, SD_CLKC_REG, clkc);
925 const uint32_t clkc = SDHC_READ(sc, SD_CLKC_REG); local in function:meson_sdhc_execute_tuning
[all...] |
