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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
amdgpu_dcn20_clk_mgr.c 113 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
135 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
137 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
170 if (clk_mgr_base->clks.dispclk_khz == 0 ||
191 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
192 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
194 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
202 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
203 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
205 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
amdgpu_rv1_clk_mgr.c 44 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
50 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz;
52 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz;
82 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold)
125 clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz;
126 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
127 clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
167 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz
168 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_kh
    [all...]
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/
imx6q-bx50v3.dtsi 397 &clks {
398 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
399 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
400 <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
401 <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
402 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
403 <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
404 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
405 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
406 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>
    [all...]
imx7d-cl-som-imx7.dts 47 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
48 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
75 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
76 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
197 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
198 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
212 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
imx6qdl-savageboard.dtsi 98 &clks {
99 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
100 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
101 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
102 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
imx6q-novena.dts 425 clocks = <&clks IMX6QDL_CLK_CKO1>;
426 assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
427 <&clks IMX6QDL_CLK_CKO1_SEL>,
428 <&clks IMX6QDL_CLK_PLL4_AUDIO>,
429 <&clks IMX6QDL_CLK_CKO1>;
430 assigned-clock-parents = <&clks IMX6QDL_CLK_CKO1>,
431 <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>,
432 <&clks IMX6QDL_CLK_OSC>,
433 <&clks IMX6QDL_CLK_CKO1_PODF>;
imx6q-pistachio.dts 169 &clks {
170 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
171 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
172 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
173 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
200 clocks = <&clks IMX6QDL_CLK_CKO>;
imx6q-cm-fx6.dts 459 assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>,
460 <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
461 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
imx6qdl-gw560x.dtsi 266 &clks {
267 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
268 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
269 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
270 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
441 clocks = <&clks IMX6QDL_CLK_CKO>;
imx6qdl-gw5903.dtsi 213 &clks {
214 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
215 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
216 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
217 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
452 clocks = <&clks IMX6QDL_CLK_CKO>;
imx53-ppd.dts 260 clocks = <&clks IMX5_CLK_CKO2>;
261 assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>;
262 assigned-clock-parents = <&clks IMX5_CLK_OSC>;
272 clocks = <&clks IMX5_CLK_CKO2>;
273 assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>;
274 assigned-clock-parents = <&clks IMX5_CLK_OSC>;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/
amdgpu_dce120_clk_mgr.c 102 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
112 clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk);
117 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) {
120 clk_mgr_base->clks.phyclk_khz = max_pix_clk;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
amdgpu_rn_clk_mgr.c 124 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
131 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
136 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
139 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
143 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
144 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
145 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
148 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
149 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
150 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz)
    [all...]
  /src/sys/arch/arm/sunxi/
sunxi_de2_ccu.c 82 struct sunxi_ccu_clk *clks; member in struct:sunxi_de2_ccu_config
89 .clks = sun8i_h3_de2_ccu_clks,
96 .clks = sun8i_h3_de2_ccu_clks,
139 sc->sc_clks = conf->clks;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_resource.c 1259 struct dm_pp_clock_levels clks = {0}; local
1265 &clks);
1268 clks.clocks_in_khz[clks.num_levels-1], 1000);
1270 clks.clocks_in_khz[clks.num_levels/8], 1000);
1272 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1274 clks.clocks_in_khz[clks.num_levels*3/8], 1000)
    [all...]
  /src/sys/arch/arm/rockchip/
rk_v1crypto.c 103 const char *const clks[]; member in struct:rk_v1crypto_data
108 .clks = {"aclk", "hclk", "sclk", "apb_pclk"},
113 .clks = {"hclk_master", "hclk_slave", "sclk"},
144 const char *const *clks = config->clks; local
164 if (fdtbus_clock_enable(phandle, clks[i], true) != 0) {
165 aprint_error(": couldn't enable %s clock\n", clks[i]);
  /src/sys/external/isc/atheros_hal/dist/ar5210/
ar5210_misc.c 440 u_int clks = OS_REG_READ(ah, AR_IFS0) & 0x7ff; local
441 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
465 u_int clks = OS_REG_READ(ah, AR_SLOT_TIME) & 0xffff; local
466 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
491 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); local
492 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
538 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); local
539 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_resource.c 1040 struct dm_pp_clock_levels clks = {0}; local
1058 &clks);
1061 clks.clocks_in_khz[clks.num_levels-1], 1000);
1063 clks.clocks_in_khz[clks.num_levels/8], 1000);
1065 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1067 clks.clocks_in_khz[clks.num_levels*3/8], 1000)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dm_helpers.h 138 struct dc_clocks *clks);
  /src/sys/external/isc/atheros_hal/dist/ar5211/
ar5211_misc.c 443 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff; local
444 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
468 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff; local
469 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
494 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); local
495 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
541 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); local
542 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
amdgpu_dce110_clk_mgr.c 235 pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
273 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
275 clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_clk_mgr.c 655 pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz;
693 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
695 clk_mgr->clks.dispclk_khz = patched_disp_clk;
720 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
722 clk_mgr->clks.dispclk_khz = patched_disp_clk;
747 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
749 clk_mgr->clks.dispclk_khz = patched_disp_clk;
767 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
777 clk_mgr->clks.dispclk_khz = dce112_set_clock(clk_mgr, patched_disp_clk);
782 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz))
    [all...]
  /src/sys/external/isc/atheros_hal/dist/
ah.c 356 u_int clks; local
360 clks = usecs * CLOCK_RATE[ath_hal_chan2wmode(ah, c)];
362 clks <<= 1;
364 clks >>= 1;
366 clks >>= 2;
368 clks = usecs * CLOCK_RATE[WIRELESS_MODE_11b];
369 return clks;
373 ath_hal_mac_usec(struct ath_hal *ah, u_int clks)
380 usec = clks / CLOCK_RATE[ath_hal_chan2wmode(ah, c)];
388 usec = clks / CLOCK_RATE[WIRELESS_MODE_11b]
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
clk_mgr.h 192 struct dc_clocks clks; member in struct:clk_mgr
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm_pp_smu.c 126 struct dm_pp_clock_levels *clks)
136 clks->num_levels = 6;
137 memmove(clks->clocks_in_khz, disp_clks_in_khz,
141 clks->num_levels = 6;
142 memmove(clks->clocks_in_khz, sclks_in_khz,
146 clks->num_levels = 2;
147 memmove(clks->clocks_in_khz, mclks_in_khz,
151 clks->num_levels = 0;

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