| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx6qp.dtsi | 12 clocks = <&clks IMX6QDL_CLK_OCRAM>;
18 clocks = <&clks IMX6QDL_CLK_OCRAM>;
26 clocks = <&clks IMX6QDL_CLK_PRE0>;
35 clocks = <&clks IMX6QDL_CLK_PRE1>;
44 clocks = <&clks IMX6QDL_CLK_PRE2>;
53 clocks = <&clks IMX6QDL_CLK_PRE3>;
61 clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
62 <&clks IMX6QDL_CLK_PRG0_AXI>;
70 clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
71 <&clks IMX6QDL_CLK_PRG1_AXI>
[all...] |
| imx27.dtsi | 72 clocks = <&clks IMX27_CLK_CPU_DIV>;
95 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
96 <&clks IMX27_CLK_DMA_AHB_GATE>;
106 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
113 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
114 <&clks IMX27_CLK_PER1_GATE>;
122 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
123 <&clks IMX27_CLK_PER1_GATE>;
131 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
132 <&clks IMX27_CLK_PER1_GATE>
537 clks: ccm@10027000{ label
[all...] |
| vfxxx.dtsi | 93 clocks = <&clks VF610_CLK_DMAMUX0>,
94 <&clks VF610_CLK_DMAMUX1>;
102 clocks = <&clks VF610_CLK_FLEXCAN0>,
103 <&clks VF610_CLK_FLEXCAN0>;
112 clocks = <&clks VF610_CLK_UART0>;
124 clocks = <&clks VF610_CLK_UART1>;
136 clocks = <&clks VF610_CLK_UART2>;
148 clocks = <&clks VF610_CLK_UART3>;
162 clocks = <&clks VF610_CLK_DSPI0>;
177 clocks = <&clks VF610_CLK_DSPI1>
440 clks: ccm@4006b000 { label in label:aips0
[all...] |
| imx6qdl-icore-1.5.dtsi | 28 clocks = <&clks IMX6QDL_CLK_ENET>,
29 <&clks IMX6QDL_CLK_ENET>,
30 <&clks IMX6QDL_CLK_ENET_REF>;
|
| imx6sx.dtsi | 84 clocks = <&clks IMX6SX_CLK_ARM>,
85 <&clks IMX6SX_CLK_PLL2_PFD2>,
86 <&clks IMX6SX_CLK_STEP>,
87 <&clks IMX6SX_CLK_PLL1_SW>,
88 <&clks IMX6SX_CLK_PLL1_SYS>;
167 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
173 clocks = <&clks IMX6SX_CLK_OCRAM>;
199 clocks = <&clks IMX6SX_CLK_GPU>,
200 <&clks IMX6SX_CLK_GPU>,
201 <&clks IMX6SX_CLK_GPU>
600 clks: clock-controller@20c4000 { label
[all...] |
| imx35.dtsi | 81 clocks = <&clks 51>;
92 clocks = <&clks 53>;
101 clocks = <&clks 9>, <&clks 70>;
110 clocks = <&clks 9>, <&clks 71>;
121 clocks = <&clks 52>;
132 clocks = <&clks 68>;
145 clocks = <&clks 35 &clks 35>
209 clks: ccm@53f80000 { label in label:aips2
[all...] |
| imx25.dtsi | 95 clocks = <&clks 48>;
106 clocks = <&clks 48>;
116 clocks = <&clks 75>, <&clks 75>;
125 clocks = <&clks 76>, <&clks 76>;
134 clocks = <&clks 120>, <&clks 57>;
143 clocks = <&clks 121>, <&clks 57>
347 clks: ccm@53f80000 { label
[all...] |
| imx1.dtsi | 51 clocks = <&clks IMX1_CLK_MCU>;
82 clocks = <&clks IMX1_CLK_HCLK>,
83 <&clks IMX1_CLK_PER1>;
91 clocks = <&clks IMX1_CLK_HCLK>,
92 <&clks IMX1_CLK_PER1>;
100 clocks = <&clks IMX1_CLK_DUMMY>,
101 <&clks IMX1_CLK_DUMMY>,
102 <&clks IMX1_CLK_PER2>;
111 clocks = <&clks IMX1_CLK_HCLK>,
112 <&clks IMX1_CLK_PER1>
199 clks: ccm@21b000 { label
[all...] |
| imx31.dtsi | 77 clocks = <&clks 33>;
87 clocks = <&clks 35>;
97 clocks = <&clks 26>;
105 clocks = <&clks 10>, <&clks 30>;
114 clocks = <&clks 10>, <&clks 31>;
123 clocks = <&clks 34>;
133 clocks = <&clks 10>, <&clks 53>
235 clks: ccm@53f80000{ label
[all...] |
| imx6q.dtsi | 42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
79 clocks = <&clks IMX6QDL_CLK_ARM>,
80 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
81 <&clks IMX6QDL_CLK_STEP>,
82 <&clks IMX6QDL_CLK_PLL1_SW>,
83 <&clks IMX6QDL_CLK_PLL1_SYS>
[all...] |
| imx51.dtsi | 83 clocks = <&clks IMX5_CLK_CPU_PODF>;
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
135 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
145 clocks = <&clks IMX5_CLK_IPU_GATE>,
146 <&clks IMX5_CLK_IPU_DI0_GATE>,
147 <&clks IMX5_CLK_IPU_DI1_GATE>;
192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
193 <&clks IMX5_CLK_DUMMY>,
194 <&clks IMX5_CLK_ESDHC1_PER_GATE>
449 clks: ccm@73fd4000{ label
[all...] |
| imx50.dtsi | 91 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
122 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
123 <&clks IMX5_CLK_DUMMY>,
124 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
134 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
135 <&clks IMX5_CLK_DUMMY>,
136 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
146 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
147 <&clks IMX5_CLK_UART3_PER_GATE>;
158 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>
338 clks: ccm@53fd4000{ label
[all...] |
| imx6sl.dtsi | 72 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
73 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
74 <&clks IMX6SL_CLK_PLL1_SYS>;
120 clocks = <&clks IMX6SL_CLK_OCRAM>;
164 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
165 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>
513 clks: clock-controller@20c4000 { label in label:aips1
[all...] |
| imx6qdl.dtsi | 163 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
172 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
173 <&clks IMX6QDL_CLK_GPMI_APB>,
174 <&clks IMX6QDL_CLK_GPMI_BCH>,
175 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
176 <&clks IMX6QDL_CLK_PER1_BCH>;
188 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
189 <&clks IMX6QDL_CLK_HDMI_ISFR>;
219 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
220 <&clks IMX6QDL_CLK_GPU3D_CORE>
684 clks: clock-controller@20c4000 { label
[all...] |
| imx6ul.dtsi | 81 clocks = <&clks IMX6UL_CLK_ARM>,
82 <&clks IMX6UL_CLK_PLL2_BUS>,
83 <&clks IMX6UL_CLK_PLL2_PFD2>,
84 <&clks IMX6UL_CA7_SECONDARY_SEL>,
85 <&clks IMX6UL_CLK_STEP>,
86 <&clks IMX6UL_CLK_PLL1_SW>,
87 <&clks IMX6UL_CLK_PLL1_SYS>;
176 clocks = <&clks IMX6UL_CLK_APBHDMA>;
187 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
188 <&clks IMX6UL_CLK_GPMI_APB>
568 clks: clock-controller@20c4000 { label
[all...] |
| imx6q-logicpd.dts | 60 &clks {
61 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
62 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
63 <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
64 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
65 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
66 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
67 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
68 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
|
| imx6sll.dtsi | 70 clocks = <&clks IMX6SLL_CLK_ARM>,
71 <&clks IMX6SLL_CLK_PLL2_PFD2>,
72 <&clks IMX6SLL_CLK_STEP>,
73 <&clks IMX6SLL_CLK_PLL1_SW>,
74 <&clks IMX6SLL_CLK_PLL1_SYS>;
161 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
162 <&clks IMX6SLL_CLK_OSC>,
163 <&clks IMX6SLL_CLK_SPDIF>,
164 <&clks IMX6SLL_CLK_DUMMY>,
165 <&clks IMX6SLL_CLK_DUMMY>
488 clks: clock-controller@20c4000 { label in label:aips1
[all...] |
| imx53.dtsi | 56 clocks = <&clks IMX5_CLK_ARM>;
121 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
129 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
146 clocks = <&clks IMX5_CLK_SATA_GATE>,
147 <&clks IMX5_CLK_SATA_REF>,
148 <&clks IMX5_CLK_AHB>;
159 clocks = <&clks IMX5_CLK_IPU_GATE>,
160 <&clks IMX5_CLK_IPU_DI0_GATE>,
161 <&clks IMX5_CLK_IPU_DI1_GATE>;
221 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>
598 clks: ccm@53fd4000{ label
[all...] |
| imx7s.dtsi | 77 clocks = <&clks IMX7D_CLK_ARM>;
98 clocks = <&clks IMX7D_USB_PHY1_CLK>;
105 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
172 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
199 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
214 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
249 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
272 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
287 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
406 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>
620 clks: clock-controller@30380000 { label
[all...] |
| pxa27x.dtsi | 35 clocks = <&clks CLK_NONE>;
42 clocks = <&clks CLK_USBHOST>;
50 clocks = <&clks CLK_PWM0>;
57 clocks = <&clks CLK_PWM1>;
64 clocks = <&clks CLK_PWM0>;
71 clocks = <&clks CLK_PWM1>;
78 clocks = <&clks CLK_PWRI2C>;
88 clocks = <&clks CLK_USB>;
96 clocks = <&clks CLK_KEYPAD>;
109 clocks = <&clks CLK_CAMERA>
131 clks: pxa2xx_clks@41300004 { label
[all...] |
| imx6dl.dtsi | 37 clocks = <&clks IMX6QDL_CLK_ARM>,
38 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
39 <&clks IMX6QDL_CLK_STEP>,
40 <&clks IMX6QDL_CLK_PLL1_SW>,
41 <&clks IMX6QDL_CLK_PLL1_SYS>;
70 clocks = <&clks IMX6QDL_CLK_ARM>,
71 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
72 <&clks IMX6QDL_CLK_STEP>,
73 <&clks IMX6QDL_CLK_PLL1_SW>,
74 <&clks IMX6QDL_CLK_PLL1_SYS>
[all...] |
| imx6ull-colibri-wifi.dtsi | 41 assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
42 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
|
| imx6q-bx50v3.dtsi | 396 &clks {
397 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
398 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
399 <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
400 <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
401 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
402 <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
403 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
404 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
405 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| amdgpu_dcn20_clk_mgr.c | 113 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
135 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
137 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
170 if (clk_mgr_base->clks.dispclk_khz == 0 ||
191 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
192 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
194 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
202 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
203 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
205 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
| amdgpu_rv1_clk_mgr.c | 44 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
50 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz;
52 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz;
82 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold)
125 clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz;
126 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
127 clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
167 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz
168 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_kh
[all...] |
