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    Searched refs:clks_cfg (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 1924 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2673 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2674 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2677 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2686 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2696 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2697 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2699 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2700 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2701 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
amdgpu_display_mode_vba.c 72 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0)
379 display_clocks_and_cfg_st *clks = &pipes[j].clks_cfg;
824 mode_lib->vba.VoltageLevel = mode_lib->vba.cache_pipes[0].clks_cfg.voltage;
834 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz;
835 mode_lib->vba.SOCCLK = mode_lib->vba.cache_pipes[0].clks_cfg.socclk_mhz;
836 if (mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz > 0.0)
837 mode_lib->vba.DISPCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz;
display_mode_structs.h 359 display_clocks_and_cfg_st clks_cfg; member in struct:_vcs_dpi_display_e2e_pipe_params_st
amdgpu_dml1_display_rq_dlg_calc.c 1005 double refclk_freq_in_mhz = e2e_pipe_param.clks_cfg.refclk_mhz;
1006 double dppclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dppclk_mhz;
1007 double dispclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dispclk_mhz;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_resource.c 990 pipes[0].clks_cfg.voltage = vlevel;
991 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
992 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1064 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1065 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1068 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1077 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 482 input.clks_cfg.dcfclk_mhz = v->dcfclk;
483 input.clks_cfg.dispclk_mhz = v->dispclk;
484 input.clks_cfg.dppclk_mhz = v->dppclk;
485 input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
486 input.clks_cfg.socclk_mhz = v->socclk;
487 input.clks_cfg.voltage = v->voltage_level;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_rq_dlg_calc_20.c 785 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
amdgpu_display_rq_dlg_calc_20v2.c 785 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_rq_dlg_calc_21.c 831 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;

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