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    Searched refs:clock_sources (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/
amdgpu_dce80_resource.c 825 if (pool->base.clock_sources[i] != NULL) {
826 dce80_clock_source_destroy(&pool->base.clock_sources[i]);
961 pool->base.clock_sources[0] =
963 pool->base.clock_sources[1] =
965 pool->base.clock_sources[2] =
973 pool->base.clock_sources[0] =
975 pool->base.clock_sources[1] =
987 if (pool->base.clock_sources[i] == NULL) {
1158 pool->base.clock_sources[0] =
1160 pool->base.clock_sources[1]
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_resource.c 795 if (pool->base.clock_sources[i] != NULL) {
796 dce112_clock_source_destroy(&pool->base.clock_sources[i]);
827 return pool->clock_sources[DCE112_CLK_SRC_PLL0];
829 return pool->clock_sources[DCE112_CLK_SRC_PLL1];
831 return pool->clock_sources[DCE112_CLK_SRC_PLL2];
833 return pool->clock_sources[DCE112_CLK_SRC_PLL3];
835 return pool->clock_sources[DCE112_CLK_SRC_PLL4];
837 return pool->clock_sources[DCE112_CLK_SRC_PLL5];
1222 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1227 pool->base.clock_sources[DCE112_CLK_SRC_PLL1]
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_resource.c 648 if (pool->base.clock_sources[i] != NULL)
650 &pool->base.clock_sources[i]);
1067 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =
1071 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =
1075 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =
1079 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =
1083 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =
1087 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =
1099 if (pool->base.clock_sources[i] == NULL) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/
amdgpu_dce100_resource.c 777 if (pool->base.clock_sources[i] != NULL)
778 dce100_clock_source_destroy(&pool->base.clock_sources[i]);
979 pool->base.clock_sources[0] =
981 pool->base.clock_sources[1] =
983 pool->base.clock_sources[2] =
991 pool->base.clock_sources[0] =
993 pool->base.clock_sources[1] =
1005 if (pool->base.clock_sources[i] == NULL) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_resource.c 994 if (pool->base.clock_sources[i] != NULL) {
995 dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
996 pool->base.clock_sources[i] = NULL;
1369 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1373 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1377 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1383 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1401 if (pool->base.clock_sources[i] == NULL) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 205 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; member in struct:resource_pool
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_resource.c 952 if (pool->base.clock_sources[i] != NULL) {
953 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
954 pool->base.clock_sources[i] = NULL;
1720 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1724 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1728 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1742 if (pool->base.clock_sources[i] == NULL) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_resource.c 834 if (pool->base.clock_sources[i] != NULL) {
835 dce110_clock_source_destroy(&pool->base.clock_sources[i]);
1360 pool->base.clock_sources[0] =
1363 pool->base.clock_sources[1] =
1379 if (pool->base.clock_sources[i] == NULL) {
amdgpu_dce110_hw_sequencer.c 1477 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1478 dc->res_pool->clock_sources[i]) == false)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 1397 if (pool->base.clock_sources[i] != NULL) {
1398 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1399 pool->base.clock_sources[i] = NULL;
3549 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3553 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3557 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3561 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3565 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3569 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3581 if (pool->base.clock_sources[i] == NULL)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_resource.c 317 if (pool->clock_sources[i] == clock_source)
2545 return pool->clock_sources[i];

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