| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_resource.c | 1061 clks.clocks_in_khz[clks.num_levels-1], 1000);
1063 clks.clocks_in_khz[clks.num_levels/8], 1000);
1065 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1067 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1069 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1071 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1073 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1075 clks.clocks_in_khz[0], 1000);
1084 clks.clocks_in_khz[0] * memory_type_multiplier, 1000);
1086 clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_resource.c | 915 eng_clks.data[i].clocks_in_khz = clk;
922 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
924 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
926 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
928 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
930 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
932 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
934 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
936 eng_clks.data[0].clocks_in_khz, 1000);
949 mem_clks.data[i].clocks_in_khz = clk
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services_types.h | 101 uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS]; member in struct:dm_pp_clock_levels
105 uint32_t clocks_in_khz; member in struct:dm_pp_clock_with_latency
115 uint32_t clocks_in_khz; member in struct:dm_pp_clock_with_voltage
257 uint32_t clocks_in_khz; member in struct:dm_pp_clock_for_voltage_req
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/ |
| amdgpu_dce120_clk_mgr.c | 111 clock_voltage_req.clocks_in_khz = patched_disp_clk;
119 clock_voltage_req.clocks_in_khz = max_pix_clk;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| dm_pp_interface.h | 172 uint32_t clocks_in_khz; member in struct:pp_clock_with_latency
182 uint32_t clocks_in_khz; member in struct:pp_clock_with_voltage
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_pp_smu.c | 137 memmove(clks->clocks_in_khz, disp_clks_in_khz,
142 memmove(clks->clocks_in_khz, sclks_in_khz,
147 memmove(clks->clocks_in_khz, mclks_in_khz,
277 dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
302 DRM_DEBUG("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
303 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
329 DRM_INFO("DM_PPLIB:\t %d in kHz, %d in mV\n", pp_clks->data[i].clocks_in_khz,
331 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 1294 int clocks_in_khz)
1298 if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
1303 if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
1306 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
1308 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
1310 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {
1316 if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
1319 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
1321 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
1323 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 85 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
86 return dc->sclk_lvls.clocks_in_khz[i];
94 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_resource.c | 1268 clks.clocks_in_khz[clks.num_levels-1], 1000);
1270 clks.clocks_in_khz[clks.num_levels/8], 1000);
1272 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1274 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1276 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1278 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1280 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1282 clks.clocks_in_khz[0], 1000);
1291 clks.clocks_in_khz[clks.num_levels-1], 1000);
1293 clks.clocks_in_khz[clks.num_levels>>1], 1000)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_clk_mgr.c | 587 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
588 return dc->sclk_lvls.clocks_in_khz[i];
596 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
776 clock_voltage_req.clocks_in_khz = patched_disp_clk;
784 clock_voltage_req.clocks_in_khz = max_pix_clk;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega12_hwmgr.c | 1731 clocks->data[i].clocks_in_khz =
1763 clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;
1792 clocks->data[i].clocks_in_khz =
1820 clocks->data[i].clocks_in_khz =
2111 i, clocks.data[i].clocks_in_khz / 1000,
2112 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2127 i, clocks.data[i].clocks_in_khz / 1000,
2128 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2145 i, clocks.data[i].clocks_in_khz / 1000,
2146 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "")
[all...] |
| amdgpu_vega20_hwmgr.c | 2778 clocks->data[i].clocks_in_khz =
2806 clocks->data[i].clocks_in_khz =
2831 clocks->data[i].clocks_in_khz =
2853 clocks->data[i].clocks_in_khz =
3294 i, clocks.data[i].clocks_in_khz / 1000,
3295 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3312 i, clocks.data[i].clocks_in_khz / 1000,
3313 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3330 i, clocks.data[i].clocks_in_khz / 1000,
3331 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "")
[all...] |
| amdgpu_smu10_hwmgr.c | 1037 clocks->data[clocks->num_levels].clocks_in_khz =
1091 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
|
| amdgpu_vega10_hwmgr.c | 4287 clocks->data[clocks->num_levels].clocks_in_khz =
4309 clocks->data[j].clocks_in_khz =
4331 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4347 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4407 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_arcturus_ppt.c | 606 clocks->data[i].clocks_in_khz =
657 clocks.data[i].clocks_in_khz / 1000,
660 clocks.data[i].clocks_in_khz / 1000,
680 i, clocks.data[i].clocks_in_khz / 1000,
683 clocks.data[i].clocks_in_khz / 1000,
703 i, clocks.data[i].clocks_in_khz / 1000,
706 clocks.data[i].clocks_in_khz / 1000,
729 clocks.data[i].clocks_in_khz / 1000,
|
| amdgpu_vega20_ppt.c | 942 clocks->data[i].clocks_in_khz =
987 clocks.data[i].clocks_in_khz / 1000,
988 (clocks.data[i].clocks_in_khz == now * 10)
1008 i, clocks.data[i].clocks_in_khz / 1000,
1009 (clocks.data[i].clocks_in_khz == now * 10)
1029 i, clocks.data[i].clocks_in_khz / 1000,
1030 (clocks.data[i].clocks_in_khz == now * 10)
1065 i, clocks.data[i].clocks_in_khz / 1000,
1066 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
1155 clocks.data[0].clocks_in_khz / 1000
[all...] |
| amdgpu_navi10_ppt.c | 1038 clocks->data[i].clocks_in_khz = freq * 1000;
1634 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1642 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1655 *clocks_in_khz = (*dpm_levels) * 1000;
1656 clocks_in_khz++;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| amdgpu_smu.h | 480 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
|
