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  /src/lib/libc/compat/arch/sparc64/sys/
compat_sigprocmask.S 59 clr %o1 /* else block no signals ... */
73 clr %o0
compat_sigpending.S 60 clr %o0
  /src/sys/arch/evbarm/ifpga/
plcom_ifpga.c 113 u_int set, clr; local in function:plcom_ifpga_set_mcr
115 set = clr = 0;
122 clr |= IFPGA_SC_CTRL_UART0RTS;
126 clr |= IFPGA_SC_CTRL_UART0DTR;
131 clr |= IFPGA_SC_CTRL_UART1RTS;
135 clr |= IFPGA_SC_CTRL_UART1DTR;
143 if (clr)
145 clr);
  /src/lib/csu/arch/sparc64/
crt0.S 54 clr %fp
55 clr %g4 ! data base for some memory models
  /src/lib/libc/compat/arch/sparc/sys/
compat_sigprocmask.S 59 ! clr %o1 ! else block no signals ...
72 clr %o0
compat_sigpending.S 60 clr %o0
  /src/lib/libc/arch/sparc/gen/
setjmp.S 70 clr %o1 /* sigprocmask(0, NULL, &sc.sc_mask) */
74 clr %o0 /* sigstack(NULL, &foo) */
_setjmp.S 59 clr %o0 ! return 0
  /src/lib/libc/arch/sparc/sys/
pipe.S 63 clr %o0
getcontext.S 47 clr [%o2 + 40 + 11 * 4] ! gr[_REG_O0] = 0
  /src/lib/libc/arch/sparc64/sys/
pipe.S 63 clr %o0
  /src/lib/libc/compat/arch/sparc/gen/
compat_setjmp.S 69 clr %o1 /* sigprocmask(SIG_BLOCK, (sigset_t *)NULL) */
73 clr %o0 /* sigaltstack(NULL, &foo) */
88 clr %o0
  /src/sys/arch/m68k/fpe/
fpu_int.c 46 int sh, clr, mask, i; local in function:fpu_intrz
65 clr = 2 - sh / 32;
68 for (i = 2; i > clr; i--) {
  /src/lib/libc/compat/arch/sparc64/gen/
compat_setjmp.S 73 clr %o1 /* sigprocmask(SIG_BLOCK, (sigset_t *)NULL, (sigset_t *)a) */
78 clr %o0 /* sigstack(NULL, &foo) */
94 clr %o0
  /src/sys/dev/rasops/
rasops1-4_putchar.h 58 (tmp) |= clr[(fb >> 31) & 1] >> bit; \
66 c = clr[1]; \
68 c = clr[0]; \
70 c = (w * clr[1] + (0xff - w) * clr[0]) >> 8; \
92 uint32_t bg, fg, lbg, rbg, clr[2], lmask, rmask, tmp; local in function:NAME
152 clr[0] = bg & COLOR_MASK;
153 clr[1] = fg & COLOR_MASK;
235 clr[0] = bg & COLOR_MASK;
236 clr[1] = fg & COLOR_MASK
    [all...]
rasops_putchar.h 49 #define SET_COLOR(p, index) *(p)++ = clr[index]
61 COLOR_TYPE c = clr[index]; \
104 COLOR_TYPE clr[2]; local in function:NAME
128 clr[0] = (COLOR_TYPE)ATTR_BG(ri, attr);
129 clr[1] = (COLOR_TYPE)ATTR_FG(ri, attr);
  /src/games/dab/
box.h 72 void clr(int e);
  /src/sys/arch/arm/nvidia/
tegra_drm.h 147 #define HDMI_SET_CLEAR(enc, reg, set, clr) \
148 tegra_reg_set_clear((enc)->bst, (enc)->bsh, (reg), (set), (clr))
154 #define DC_SET_CLEAR(crtc, reg, set, clr) \
155 tegra_reg_set_clear((crtc)->bst, (crtc)->bsh, (reg), (set), (clr))
  /src/lib/libc/arch/sparc64/gen/
setjmp.S 96 clr %o1
98 clr %o0 /* sigstack(NULL, &foo) */
_setjmp.S 73 clr %o0 ! return 0
  /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/
nouveau_dispnv50_head.c 42 union nv50_head_atom_mask clr = { local in function:nv50_head_flush_clr
43 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),
45 if (clr.olut) head->func->olut_clr(head);
46 if (clr.core) head->func->core_clr(head);
47 if (clr.curs) head->func->curs_clr(head);
386 asyh->clr.core = true;
394 asyh->clr.curs = true;
402 asyh->clr.olut = true;
405 asyh->clr.olut = armh->olut.visible;
406 asyh->clr.core = armh->core.visible
    [all...]
  /src/sys/arch/m68k/060sp/dist/
itest.s 90 clr.l TESTCTR(%a6)
100 clr.l TESTCTR(%a6)
110 clr.l TESTCTR(%a6)
120 clr.l TESTCTR(%a6)
130 clr.l TESTCTR(%a6)
141 clr.l TESTCTR(%a6)
151 clr.l TESTCTR(%a6)
178 clr.l %d1
190 clr.l IREGS+0x8(%a6)
191 clr.l IREGS+0xc(%a6
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/core/
nouveau_nvkm_core_memory.c 54 u32 nr, void (*clr)(struct nvkm_device *, u32, u32),
83 if (clr)
84 clr(device, tags->mn->offset, tags->mn->length);
  /src/common/dist/zlib/examples/
gzjoin.c 273 block if clr is true, and adding empty blocks as needed to get to a byte
274 boundary. If clr is false, then the last block becomes the last block of
279 local void gzcopy(char *name, int clr, unsigned long *crc, unsigned long *tot,
314 if (last && clr)
354 if (last && clr)
367 if (last && clr)
381 if (pos == 0 || !clr)
420 if (!clr) {
  /src/sys/arch/sparc64/sparc64/
db_tlb_access.S 41 clr %l2
75 clr %l2
116 clr %l2
158 clr %l2

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