1 /* $NetBSD: com.c,v 1.389 2025/10/24 23:16:11 brad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 * 67 * Lock order (when sc_softirq is false): 68 * ttylock (IPL_VM) 69 * -> sc->sc_lock (IPL_HIGH) 70 * -> timecounter_lock (IPL_HIGH) 71 * 72 * When sc_softirq is true, the ttylock is dropped or avoided and 73 * sc->sc_lock is run at IPL_SOFTSERIAL 74 * 75 */ 76 77 #include <sys/cdefs.h> 78 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.389 2025/10/24 23:16:11 brad Exp $"); 79 80 #include "opt_com.h" 81 #include "opt_ddb.h" 82 #include "opt_kgdb.h" 83 #include "opt_lockdebug.h" 84 #include "opt_multiprocessor.h" 85 #include "opt_ntp.h" 86 87 /* The COM16650 option was renamed to COM_16650. */ 88 #ifdef COM16650 89 #error Obsolete COM16650 option; use COM_16650 instead. 90 #endif 91 92 /* 93 * Override cnmagic(9) macro before including <sys/systm.h>. 94 * We need to know if cn_check_magic triggered debugger, so set a flag. 95 * Callers of cn_check_magic must declare int cn_trapped = 0; 96 * XXX: this is *ugly*! 97 */ 98 #define cn_trap() \ 99 do { \ 100 console_debugger(); \ 101 cn_trapped = 1; \ 102 (void)cn_trapped; \ 103 } while (/* CONSTCOND */ 0) 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/ioctl.h> 108 #include <sys/select.h> 109 #include <sys/poll.h> 110 #include <sys/tty.h> 111 #include <sys/proc.h> 112 #include <sys/conf.h> 113 #include <sys/file.h> 114 #include <sys/uio.h> 115 #include <sys/kernel.h> 116 #include <sys/syslog.h> 117 #include <sys/device.h> 118 #include <sys/malloc.h> 119 #include <sys/timepps.h> 120 #include <sys/vnode.h> 121 #include <sys/kauth.h> 122 #include <sys/intr.h> 123 #include <sys/workqueue.h> 124 #ifdef RND_COM 125 #include <sys/rndsource.h> 126 #endif 127 128 #include <sys/bus.h> 129 130 #include <ddb/db_active.h> 131 132 #include <dev/ic/comreg.h> 133 #include <dev/ic/comvar.h> 134 #include <dev/ic/ns16550reg.h> 135 #include <dev/ic/st16650reg.h> 136 #include <dev/ic/hayespreg.h> 137 #define com_lcr com_cfcr 138 #include <dev/cons.h> 139 140 #include "ioconf.h" 141 142 #define CSR_READ_1(r, o) \ 143 (r)->cr_read((r), (r)->cr_map[o]) 144 #define CSR_WRITE_1(r, o, v) \ 145 (r)->cr_write((r), (r)->cr_map[o], (v)) 146 #define CSR_WRITE_MULTI(r, o, p, n) \ 147 (r)->cr_write_multi((r), (r)->cr_map[o], (p), (n)) 148 149 /* 150 * XXX COM_TYPE_AU1x00 specific 151 */ 152 #define CSR_WRITE_2(r, o, v) \ 153 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 154 #define CSR_READ_2(r, o) \ 155 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 156 157 static void com_enable_debugport(struct com_softc *); 158 159 void com_config(struct com_softc *); 160 void com_shutdown(struct com_softc *); 161 int comspeed(long, long, int); 162 static u_char cflag2lcr(tcflag_t); 163 int comparam(struct tty *, struct termios *); 164 void comstart(struct tty *); 165 void comstartsoft(struct tty *); 166 int comhwiflow(struct tty *, int); 167 int comhwiflowsoft(struct tty *, int); 168 169 void com_loadchannelregs(struct com_softc *); 170 void com_hwiflow(struct com_softc *); 171 void com_break(struct com_softc *, int); 172 void com_modem(struct com_softc *, int); 173 void tiocm_to_com(struct com_softc *, u_long, int); 174 int com_to_tiocm(struct com_softc *); 175 void com_iflush(struct com_softc *); 176 177 int com_common_getc(dev_t, struct com_regs *); 178 static void com_common_putc(dev_t, struct com_regs *, int, int); 179 180 int cominit(struct com_regs *, int, int, int, tcflag_t); 181 182 static int comcnreattach(void); 183 184 int comcngetc(dev_t); 185 void comcnputc(dev_t, int); 186 void comcnpollc(dev_t, int); 187 188 void comsoft(void *); 189 static void comsoftwq(struct work *, void *); 190 static inline void com_rxsoft(struct com_softc *, struct tty *); 191 static inline void com_txsoft(struct com_softc *, struct tty *); 192 static inline void com_stsoft(struct com_softc *, struct tty *); 193 static inline void com_schedrx(struct com_softc *); 194 void comdiag(void *); 195 196 dev_type_open(comopen); 197 dev_type_close(comclose); 198 dev_type_read(comread); 199 dev_type_write(comwrite); 200 dev_type_ioctl(comioctl); 201 dev_type_stop(comstop); 202 dev_type_tty(comtty); 203 dev_type_poll(compoll); 204 205 static struct comcons_info comcons_info; 206 207 /* 208 * Following are all routines needed for COM to act as console 209 */ 210 static struct consdev comcons = { 211 .cn_getc = comcngetc, 212 .cn_putc = comcnputc, 213 .cn_pollc = comcnpollc, 214 .cn_dev = NODEV, 215 .cn_pri = CN_NORMAL 216 }; 217 218 219 const struct cdevsw com_cdevsw = { 220 .d_open = comopen, 221 .d_close = comclose, 222 .d_read = comread, 223 .d_write = comwrite, 224 .d_ioctl = comioctl, 225 .d_stop = comstop, 226 .d_tty = comtty, 227 .d_poll = compoll, 228 .d_mmap = nommap, 229 .d_kqfilter = ttykqfilter, 230 .d_discard = nodiscard, 231 .d_flag = D_TTY 232 }; 233 234 /* 235 * Make this an option variable one can patch. 236 * But be warned: this must be a power of 2! 237 */ 238 u_int com_rbuf_size = COM_RING_SIZE; 239 240 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 241 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 242 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 243 244 static int comconsattached; 245 static struct cnm_state com_cnm_state; 246 247 #ifdef KGDB 248 #include <sys/kgdb.h> 249 250 static struct com_regs comkgdbregs; 251 static int com_kgdb_attached; 252 253 int com_kgdb_getc(void *); 254 void com_kgdb_putc(void *, int); 255 #endif /* KGDB */ 256 257 /* initializer for typical 16550-ish hardware */ 258 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 259 [COM_REG_RXDATA] = com_data, 260 [COM_REG_TXDATA] = com_data, 261 [COM_REG_DLBL] = com_dlbl, 262 [COM_REG_DLBH] = com_dlbh, 263 [COM_REG_IER] = com_ier, 264 [COM_REG_IIR] = com_iir, 265 [COM_REG_FIFO] = com_fifo, 266 [COM_REG_TCR] = com_fifo, 267 [COM_REG_EFR] = com_efr, 268 [COM_REG_TLR] = com_efr, 269 [COM_REG_LCR] = com_lcr, 270 [COM_REG_MCR] = com_mcr, 271 [COM_REG_LSR] = com_lsr, 272 [COM_REG_MSR] = com_msr, 273 [COM_REG_USR] = com_usr, 274 [COM_REG_TFL] = com_tfl, 275 [COM_REG_RFL] = com_rfl, 276 [COM_REG_HALT] = com_halt, 277 [COM_REG_MDR1] = com_mdr1, 278 }; 279 280 #define COMDIALOUT_MASK TTDIALOUT_MASK 281 282 #define COMUNIT(x) TTUNIT(x) 283 #define COMDIALOUT(x) TTDIALOUT(x) 284 285 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 286 device_is_active((sc)->sc_dev)) 287 288 #define BR BUS_SPACE_BARRIER_READ 289 #define BW BUS_SPACE_BARRIER_WRITE 290 #define COM_BARRIER(r, f) \ 291 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 292 293 /* Wrap the mutex calls to pick which varient we need to be using */ 294 295 static void 296 com_mutex_enter(struct com_softc *sc) 297 { 298 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 299 mutex_enter(&sc->sc_lock); 300 else 301 mutex_spin_enter(&sc->sc_lock); 302 } 303 304 static void 305 com_mutex_exit(struct com_softc *sc) 306 { 307 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 308 mutex_exit(&sc->sc_lock); 309 else 310 mutex_spin_exit(&sc->sc_lock); 311 } 312 313 /* 314 * com_read_1 -- 315 * Default register read callback using single byte accesses. 316 */ 317 static uint8_t 318 com_read_1(struct com_regs *regs, u_int reg) 319 { 320 return bus_space_read_1(regs->cr_iot, regs->cr_ioh, reg); 321 } 322 323 /* 324 * com_write_1 -- 325 * Default register write callback using single byte accesses. 326 */ 327 static void 328 com_write_1(struct com_regs *regs, u_int reg, uint8_t val) 329 { 330 bus_space_write_1(regs->cr_iot, regs->cr_ioh, reg, val); 331 } 332 333 /* 334 * com_write_multi_1 -- 335 * Default register multi write callback using single byte accesses. 336 */ 337 static void 338 com_write_multi_1(struct com_regs *regs, u_int reg, const uint8_t *datap, 339 bus_size_t count) 340 { 341 bus_space_write_multi_1(regs->cr_iot, regs->cr_ioh, reg, datap, count); 342 } 343 344 /* 345 * com_read_4 -- 346 * Default register read callback using dword accesses. 347 */ 348 static uint8_t 349 com_read_4(struct com_regs *regs, u_int reg) 350 { 351 return bus_space_read_4(regs->cr_iot, regs->cr_ioh, reg) & 0xff; 352 } 353 354 /* 355 * com_write_4 -- 356 * Default register write callback using dword accesses. 357 */ 358 static void 359 com_write_4(struct com_regs *regs, u_int reg, uint8_t val) 360 { 361 bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, val); 362 } 363 364 /* 365 * com_write_multi_4 -- 366 * Default register multi write callback using dword accesses. 367 */ 368 static void 369 com_write_multi_4(struct com_regs *regs, u_int reg, const uint8_t *datap, 370 bus_size_t count) 371 { 372 while (count-- > 0) { 373 bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, *datap++); 374 } 375 } 376 377 /* 378 * com_init_regs -- 379 * Driver front-ends use this to initialize our register map 380 * in the standard fashion. They may then tailor the map to 381 * their own particular requirements. 382 */ 383 void 384 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 385 bus_addr_t addr) 386 { 387 388 memset(regs, 0, sizeof(*regs)); 389 regs->cr_iot = st; 390 regs->cr_ioh = sh; 391 regs->cr_iobase = addr; 392 regs->cr_nports = COM_NPORTS; 393 regs->cr_read = com_read_1; 394 regs->cr_write = com_write_1; 395 regs->cr_write_multi = com_write_multi_1; 396 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 397 } 398 399 /* 400 * com_init_regs_stride -- 401 * Convenience function for front-ends that have a stride between 402 * registers. 403 */ 404 void 405 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 406 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 407 { 408 409 com_init_regs(regs, st, sh, addr); 410 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 411 regs->cr_map[i] <<= regshift; 412 } 413 regs->cr_nports <<= regshift; 414 } 415 416 /* 417 * com_init_regs_stride_width -- 418 * Convenience function for front-ends that have a stride between 419 * registers and specific I/O width requirements. 420 */ 421 void 422 com_init_regs_stride_width(struct com_regs *regs, bus_space_tag_t st, 423 bus_space_handle_t sh, bus_addr_t addr, 424 u_int regshift, u_int width) 425 { 426 427 com_init_regs(regs, st, sh, addr); 428 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 429 regs->cr_map[i] <<= regshift; 430 } 431 regs->cr_nports <<= regshift; 432 433 switch (width) { 434 case 1: 435 /* Already set by com_init_regs */ 436 break; 437 case 4: 438 regs->cr_read = com_read_4; 439 regs->cr_write = com_write_4; 440 regs->cr_write_multi = com_write_multi_4; 441 break; 442 default: 443 panic("com: unsupported I/O width %d", width); 444 } 445 } 446 447 /*ARGSUSED*/ 448 int 449 comspeed(long speed, long frequency, int type) 450 { 451 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 452 453 int x, err; 454 int divisor = 16; 455 456 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 457 divisor = 13; 458 } 459 460 if (speed == 0) 461 return (0); 462 if (speed < 0) 463 return (-1); 464 x = divrnd(frequency / divisor, speed); 465 if (x <= 0) 466 return (-1); 467 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 468 if (err < 0) 469 err = -err; 470 if (err > COM_TOLERANCE) 471 return (-1); 472 if (x > 65535) /* There are only 16 bits for the divider. */ 473 return (-1); 474 return (x); 475 476 #undef divrnd 477 } 478 479 #ifdef COM_DEBUG 480 int com_debug = 0; 481 482 void comstatus(struct com_softc *, const char *); 483 void 484 comstatus(struct com_softc *sc, const char *str) 485 { 486 struct tty *tp = sc->sc_tty; 487 488 aprint_normal_dev(sc->sc_dev, 489 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 490 str, 491 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 492 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 493 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 494 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 495 sc->sc_tx_stopped ? '+' : '-'); 496 497 aprint_normal_dev(sc->sc_dev, 498 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 499 str, 500 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 501 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 502 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 503 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 504 sc->sc_rx_flags); 505 } 506 #endif 507 508 int 509 com_probe_subr(struct com_regs *regs) 510 { 511 512 /* force access to id reg */ 513 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 514 CSR_WRITE_1(regs, COM_REG_IIR, 0); 515 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 516 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 517 return (0); 518 519 return (1); 520 } 521 522 int 523 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 524 { 525 struct com_regs regs; 526 527 com_init_regs(®s, iot, ioh, 0/*XXX*/); 528 529 return com_probe_subr(®s); 530 } 531 532 /* 533 * No locking in this routine; it is only called during attach, 534 * or with the port already locked. 535 */ 536 static void 537 com_enable_debugport(struct com_softc *sc) 538 { 539 540 /* Turn on line break interrupt, set carrier. */ 541 sc->sc_ier = IER_ERLS; 542 if (sc->sc_type == COM_TYPE_PXA2x0) 543 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 544 if (sc->sc_type == COM_TYPE_INGENIC || 545 sc->sc_type == COM_TYPE_TEGRA) 546 sc->sc_ier |= IER_ERXTOUT; 547 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 548 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 549 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 550 } 551 552 static void 553 com_intr_poll(void *arg) 554 { 555 struct com_softc * const sc = arg; 556 557 comintr(sc); 558 559 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 560 } 561 562 void 563 com_attach_subr(struct com_softc *sc) 564 { 565 struct com_regs *regsp = &sc->sc_regs; 566 struct tty *tp; 567 uint32_t cpr; 568 uint8_t lcr; 569 const char *fifo_msg = NULL; 570 prop_dictionary_t dict; 571 bool is_console = true; 572 bool force_console = false; 573 bool skip_attach_delay = false; 574 int error; 575 aprint_naive("\n"); 576 577 dict = device_properties(sc->sc_dev); 578 prop_dictionary_get_bool(dict, "is_console", &is_console); 579 prop_dictionary_get_bool(dict, "force_console", &force_console); 580 prop_dictionary_get_bool(dict, "skip_attach_delay", &skip_attach_delay); 581 callout_init(&sc->sc_diag_callout, 0); 582 583 /* The softirq case must run everything here at IPL_SOFTfoo and 584 * not have any spin locks involved 585 */ 586 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) { 587 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTSERIAL); 588 } else { 589 callout_init(&sc->sc_poll_callout, 0); 590 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 591 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 592 } 593 594 #if defined(COM_16650) 595 sc->sc_type = COM_TYPE_16650; 596 #elif defined(COM_16750) 597 sc->sc_type = COM_TYPE_16750; 598 #elif defined(COM_HAYESP) 599 sc->sc_type = COM_TYPE_HAYESP; 600 #elif defined(COM_PXA2X0) 601 sc->sc_type = COM_TYPE_PXA2x0; 602 #endif 603 604 /* Disable interrupts before configuring the device. */ 605 if (sc->sc_type == COM_TYPE_PXA2x0) 606 sc->sc_ier = IER_EUART; 607 else 608 sc->sc_ier = 0; 609 610 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 611 612 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 613 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 614 comconsattached = 1; 615 616 if (force_console) 617 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 618 619 if (cn_tab == NULL && comcnreattach() != 0) { 620 printf("can't re-init serial console @%lx\n", 621 (u_long)comcons_info.regs.cr_iobase); 622 } 623 624 switch (sc->sc_type) { 625 case COM_TYPE_16750: 626 case COM_TYPE_DW_APB: 627 /* Use in comintr(). */ 628 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 629 break; 630 } 631 632 /* No need for a delay on virtual machines. */ 633 if (!skip_attach_delay) 634 delay(10000); /* wait for output to finish */ 635 636 /* Make sure the console is always "hardwired". */ 637 if (is_console) { 638 SET(sc->sc_hwflags, COM_HW_CONSOLE); 639 } 640 641 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 642 } 643 644 /* Probe for FIFO */ 645 switch (sc->sc_type) { 646 case COM_TYPE_HAYESP: 647 goto fifodone; 648 649 case COM_TYPE_AU1x00: 650 sc->sc_fifolen = 16; 651 fifo_msg = "Au1X00 UART"; 652 SET(sc->sc_hwflags, COM_HW_FIFO); 653 goto fifodelay; 654 655 case COM_TYPE_16550_NOERS: 656 sc->sc_fifolen = 16; 657 fifo_msg = "ns16650, no ERS"; 658 SET(sc->sc_hwflags, COM_HW_FIFO); 659 goto fifodelay; 660 661 case COM_TYPE_OMAP: 662 sc->sc_fifolen = 64; 663 fifo_msg = "OMAP UART"; 664 SET(sc->sc_hwflags, COM_HW_FIFO); 665 goto fifodelay; 666 667 case COM_TYPE_INGENIC: 668 sc->sc_fifolen = 16; 669 fifo_msg = "Ingenic UART"; 670 SET(sc->sc_hwflags, COM_HW_FIFO); 671 SET(sc->sc_hwflags, COM_HW_NOIEN); 672 goto fifodelay; 673 674 case COM_TYPE_TEGRA: 675 sc->sc_fifolen = 8; 676 fifo_msg = "Tegra UART"; 677 SET(sc->sc_hwflags, COM_HW_FIFO); 678 CSR_WRITE_1(regsp, COM_REG_FIFO, 679 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 680 goto fifodelay; 681 682 case COM_TYPE_BCMAUXUART: 683 sc->sc_fifolen = 1; 684 fifo_msg = "BCM AUX UART"; 685 SET(sc->sc_hwflags, COM_HW_FIFO); 686 CSR_WRITE_1(regsp, COM_REG_FIFO, 687 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 688 goto fifodelay; 689 690 case COM_TYPE_DW_APB: 691 if (!prop_dictionary_get_uint(dict, "fifolen", &sc->sc_fifolen)) { 692 cpr = bus_space_read_4(sc->sc_regs.cr_iot, 693 sc->sc_regs.cr_ioh, DW_APB_UART_CPR); 694 sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16; 695 } 696 if (sc->sc_fifolen == 0) { 697 sc->sc_fifolen = 1; 698 fifo_msg = "DesignWare APB UART, no fifo"; 699 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 700 } else { 701 fifo_msg = "DesignWare APB UART"; 702 SET(sc->sc_hwflags, COM_HW_FIFO); 703 CSR_WRITE_1(regsp, COM_REG_FIFO, 704 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 705 } 706 goto fifodelay; 707 708 case COM_TYPE_SC16IS7XX: 709 sc->sc_fifolen = 64; 710 fifo_msg = "NXP UART"; 711 SET(sc->sc_hwflags, COM_HW_FLOW); 712 SET(sc->sc_hwflags, COM_HW_FIFO); 713 SET(sc->sc_hwflags, COM_HW_MCRPRESCALE); 714 CSR_WRITE_1(regsp, COM_REG_FIFO, 715 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 716 goto fifodelay; 717 } 718 719 sc->sc_fifolen = 1; 720 /* look for a NS 16550AF UART with FIFOs */ 721 if (sc->sc_type == COM_TYPE_INGENIC) { 722 CSR_WRITE_1(regsp, COM_REG_FIFO, 723 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 724 FIFO_TRIGGER_14 | FIFO_UART_ON); 725 } else 726 CSR_WRITE_1(regsp, COM_REG_FIFO, 727 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 728 delay(100); 729 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 730 == IIR_FIFO_MASK) 731 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 732 == FIFO_TRIGGER_14) { 733 SET(sc->sc_hwflags, COM_HW_FIFO); 734 735 fifo_msg = "ns16550a"; 736 sc->sc_fifolen = 16; 737 738 /* 739 * IIR changes into the EFR if LCR is set to LCR_EERS 740 * on 16650s. We also know IIR != 0 at this point. 741 * Write 0 into the EFR, and read it. If the result 742 * is 0, we have a 16650. 743 * 744 * Older 16650s were broken; the test to detect them 745 * is taken from the Linux driver. Apparently 746 * setting DLAB enable gives access to the EFR on 747 * these chips. 748 */ 749 if (sc->sc_type == COM_TYPE_16650) { 750 lcr = CSR_READ_1(regsp, COM_REG_LCR); 751 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 752 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 753 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 754 CSR_WRITE_1(regsp, COM_REG_LCR, 755 lcr | LCR_DLAB); 756 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 757 CLR(sc->sc_hwflags, COM_HW_FIFO); 758 sc->sc_fifolen = 0; 759 } else { 760 SET(sc->sc_hwflags, COM_HW_FLOW); 761 sc->sc_fifolen = 32; 762 } 763 } else 764 sc->sc_fifolen = 16; 765 766 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 767 if (sc->sc_fifolen == 0) 768 fifo_msg = "st16650, broken fifo"; 769 else if (sc->sc_fifolen == 32) 770 fifo_msg = "st16650a"; 771 else 772 fifo_msg = "ns16550a"; 773 } 774 775 /* 776 * TL16C750 can enable 64byte FIFO, only when DLAB 777 * is 1. However, some 16750 may always enable. For 778 * example, restrictions according to DLAB in a data 779 * sheet for SC16C750 were not described. 780 * Please enable 'options COM_16650', supposing you 781 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 782 * should become effective. 783 */ 784 if (sc->sc_type == COM_TYPE_16750) { 785 uint8_t iir1, iir2; 786 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 787 788 lcr = CSR_READ_1(regsp, COM_REG_LCR); 789 CSR_WRITE_1(regsp, COM_REG_LCR, 790 lcr & ~LCR_DLAB); 791 CSR_WRITE_1(regsp, COM_REG_FIFO, 792 fcr | FIFO_64B_ENABLE); 793 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 794 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 795 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 796 CSR_WRITE_1(regsp, COM_REG_FIFO, 797 fcr | FIFO_64B_ENABLE); 798 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 799 800 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 801 802 if (!ISSET(iir1, IIR_64B_FIFO) && 803 ISSET(iir2, IIR_64B_FIFO)) { 804 /* It is TL16C750. */ 805 sc->sc_fifolen = 64; 806 SET(sc->sc_hwflags, COM_HW_AFE); 807 } else 808 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 809 810 if (sc->sc_fifolen == 64) 811 fifo_msg = "tl16c750"; 812 else 813 fifo_msg = "ns16750"; 814 } 815 } else 816 fifo_msg = "ns16550, broken fifo"; 817 else 818 fifo_msg = "ns8250 or ns16450, no fifo"; 819 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 820 821 fifodelay: 822 /* 823 * Some chips will clear down both Tx and Rx FIFOs when zero is 824 * written to com_fifo. If this chip is the console, writing zero 825 * results in some of the chip/FIFO description being lost, so delay 826 * printing it until now. 827 */ 828 delay(10); 829 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 830 aprint_normal(": %s, %d-byte FIFO\n", fifo_msg, sc->sc_fifolen); 831 } else { 832 aprint_normal(": %s\n", fifo_msg); 833 } 834 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 835 sc->sc_fifolen = 1; 836 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 837 } 838 839 fifodone: 840 841 tp = tty_alloc(); 842 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) { 843 tp->t_oproc = comstartsoft; 844 tp->t_hwiflow = comhwiflowsoft; 845 } else { 846 tp->t_oproc = comstart; 847 tp->t_hwiflow = comhwiflow; 848 } 849 tp->t_param = comparam; 850 tp->t_softc = sc; 851 852 sc->sc_tty = tp; 853 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 854 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 855 sc->sc_rbavail = com_rbuf_size; 856 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 857 858 tty_attach(tp); 859 860 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 861 SET(sc->sc_mcr, MCR_IENABLE); 862 863 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 864 int maj; 865 866 /* locate the major number */ 867 maj = cdevsw_lookup_major(&com_cdevsw); 868 869 tp->t_dev = cn_tab->cn_dev = makedev(maj, 870 device_unit(sc->sc_dev)); 871 872 aprint_normal_dev(sc->sc_dev, "console\n"); 873 } 874 875 #ifdef KGDB 876 /* 877 * Allow kgdb to "take over" this port. If this is 878 * not the console and is the kgdb device, it has 879 * exclusive use. If it's the console _and_ the 880 * kgdb device, it doesn't. 881 */ 882 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 883 regsp->cr_iobase == comkgdbregs.cr_iobase) { 884 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 885 com_kgdb_attached = 1; 886 887 SET(sc->sc_hwflags, COM_HW_KGDB); 888 } 889 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 890 } 891 #endif 892 893 /* Use a workqueue in the softirq case and not a softint, which 894 * tripped panics 895 */ 896 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) { 897 error = workqueue_create(&sc->sc_wq, device_xname(sc->sc_dev), 898 comsoftwq, sc, PRI_SOFTSERIAL, IPL_SOFTSERIAL, WQ_MPSAFE); 899 if (error) { 900 aprint_error_dev(sc->sc_dev, 901 "Could not create workqueue: %d\n", 902 error); 903 } 904 sc->sc_si = NULL; 905 } else { 906 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 907 sc->sc_wq = NULL; 908 } 909 910 #ifdef RND_COM 911 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 912 RND_TYPE_TTY, RND_FLAG_DEFAULT); 913 #endif 914 915 /* if there are no enable/disable functions, assume the device 916 is always enabled */ 917 if (!sc->enable) 918 sc->enabled = 1; 919 920 com_config(sc); 921 922 SET(sc->sc_hwflags, COM_HW_DEV_OK); 923 924 /* A choice was made here... in the softirq case, have the code that 925 * this is glued to start the interrupt poller. The SC16IS7XX needs this 926 * because there are two ports on one chip with a single interrupt and you 927 * wouldn't want two kernel threads running to do that artifical interrupt. 928 */ 929 if (sc->sc_poll_ticks != 0) { 930 if (!ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) { 931 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 932 } 933 } 934 } 935 936 void 937 com_config(struct com_softc *sc) 938 { 939 struct com_regs *regsp = &sc->sc_regs; 940 941 /* Disable interrupts before configuring the device. */ 942 if (sc->sc_type == COM_TYPE_PXA2x0) 943 sc->sc_ier = IER_EUART; 944 else 945 sc->sc_ier = 0; 946 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 947 (void) CSR_READ_1(regsp, COM_REG_IIR); 948 949 /* Look for a Hayes ESP board. */ 950 if (sc->sc_type == COM_TYPE_HAYESP) { 951 952 /* Set 16550 compatibility mode */ 953 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 954 HAYESP_SETMODE); 955 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 956 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 957 HAYESP_MODE_SCALE); 958 959 /* Set RTS/CTS flow control */ 960 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 961 HAYESP_SETFLOWTYPE); 962 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 963 HAYESP_FLOW_RTS); 964 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 965 HAYESP_FLOW_CTS); 966 967 /* Set flow control levels */ 968 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 969 HAYESP_SETRXFLOW); 970 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 971 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 972 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 973 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 974 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 975 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 976 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 977 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 978 } 979 980 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 981 com_enable_debugport(sc); 982 } 983 984 int 985 com_detach(device_t self, int flags) 986 { 987 struct com_softc *sc = device_private(self); 988 int maj, mn; 989 990 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 991 return EBUSY; 992 993 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 994 (flags & DETACH_SHUTDOWN) != 0) 995 return EBUSY; 996 997 if (sc->disable != NULL && sc->enabled != 0) { 998 (*sc->disable)(sc); 999 sc->enabled = 0; 1000 } 1001 1002 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1003 comconsattached = 0; 1004 cn_tab = NULL; 1005 } 1006 1007 /* locate the major number */ 1008 maj = cdevsw_lookup_major(&com_cdevsw); 1009 1010 /* Nuke the vnodes for any open instances. */ 1011 mn = device_unit(self); 1012 vdevgone(maj, mn, mn, VCHR); 1013 1014 mn |= COMDIALOUT_MASK; 1015 vdevgone(maj, mn, mn, VCHR); 1016 1017 if (sc->sc_rbuf == NULL) { 1018 /* 1019 * Ring buffer allocation failed in the com_attach_subr, 1020 * only the tty is allocated, and nothing else. 1021 */ 1022 tty_free(sc->sc_tty); 1023 return 0; 1024 } 1025 1026 /* Free the receive buffer. */ 1027 free(sc->sc_rbuf, M_DEVBUF); 1028 1029 /* Detach and free the tty. */ 1030 tty_detach(sc->sc_tty); 1031 tty_free(sc->sc_tty); 1032 1033 /* Unhook the soft interrupt handler. */ 1034 if (sc->sc_si != NULL) 1035 softint_disestablish(sc->sc_si); 1036 1037 if (sc->sc_wq != NULL) 1038 workqueue_destroy(sc->sc_wq); 1039 1040 #ifdef RND_COM 1041 /* Unhook the entropy source. */ 1042 rnd_detach_source(&sc->rnd_source); 1043 #endif 1044 callout_destroy(&sc->sc_diag_callout); 1045 /* XXX - missing callout_destroy for sc->sc_poll_callout ??? */ 1046 1047 /* Destroy the lock. */ 1048 mutex_destroy(&sc->sc_lock); 1049 1050 return (0); 1051 } 1052 1053 void 1054 com_shutdown(struct com_softc *sc) 1055 { 1056 struct tty *tp = sc->sc_tty; 1057 1058 com_mutex_enter(sc); 1059 1060 /* If we were asserting flow control, then deassert it. */ 1061 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1062 com_hwiflow(sc); 1063 1064 /* Clear any break condition set with TIOCSBRK. */ 1065 com_break(sc, 0); 1066 1067 /* 1068 * Hang up if necessary. Record when we hung up, so if we 1069 * immediately open the port again, we will wait a bit until 1070 * the other side has had time to notice that we hung up. 1071 */ 1072 if (ISSET(tp->t_cflag, HUPCL)) { 1073 com_modem(sc, 0); 1074 microuptime(&sc->sc_hup_pending); 1075 sc->sc_hup_pending.tv_sec++; 1076 } 1077 1078 /* Turn off interrupts. */ 1079 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1080 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 1081 if ((sc->sc_type == COM_TYPE_PXA2x0) || 1082 (sc->sc_type == COM_TYPE_INGENIC) || 1083 (sc->sc_type == COM_TYPE_TEGRA)) 1084 sc->sc_ier |= IER_ERXTOUT; 1085 } else 1086 sc->sc_ier = 0; 1087 1088 if (sc->sc_type == COM_TYPE_PXA2x0) 1089 sc->sc_ier |= IER_EUART; 1090 1091 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1092 1093 com_mutex_exit(sc); 1094 1095 if (sc->disable) { 1096 #ifdef DIAGNOSTIC 1097 if (!sc->enabled) 1098 panic("com_shutdown: not enabled?"); 1099 #endif 1100 (*sc->disable)(sc); 1101 sc->enabled = 0; 1102 } 1103 } 1104 1105 int 1106 comopen(dev_t dev, int flag, int mode, struct lwp *l) 1107 { 1108 struct com_softc *sc; 1109 struct tty *tp; 1110 int s; 1111 int error; 1112 1113 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1114 1115 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 1116 sc->sc_rbuf == NULL) 1117 return (ENXIO); 1118 1119 if (!device_is_active(sc->sc_dev)) 1120 return (ENXIO); 1121 1122 #ifdef KGDB 1123 /* 1124 * If this is the kgdb port, no other use is permitted. 1125 */ 1126 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 1127 return (EBUSY); 1128 #endif 1129 1130 tp = sc->sc_tty; 1131 1132 /* 1133 * If the device is exclusively for kernel use, deny userland 1134 * open. 1135 */ 1136 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1137 return (EBUSY); 1138 1139 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 1140 return (EBUSY); 1141 1142 /* Run at the IPL_SOFTfoo level */ 1143 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 1144 s = splsoftserial(); 1145 else 1146 s = spltty(); 1147 1148 /* 1149 * Do the following iff this is a first open. 1150 */ 1151 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1152 struct termios t; 1153 struct timeval now, diff; 1154 1155 tp->t_dev = dev; 1156 1157 if (sc->enable) { 1158 if ((*sc->enable)(sc)) { 1159 splx(s); 1160 aprint_error_dev(sc->sc_dev, 1161 "device enable failed\n"); 1162 return (EIO); 1163 } 1164 com_mutex_enter(sc); 1165 sc->enabled = 1; 1166 com_config(sc); 1167 } else { 1168 com_mutex_enter(sc); 1169 } 1170 1171 if (timerisset(&sc->sc_hup_pending)) { 1172 microuptime(&now); 1173 while (timercmp(&now, &sc->sc_hup_pending, <)) { 1174 timersub(&sc->sc_hup_pending, &now, &diff); 1175 const int ms = diff.tv_sec * 1000 + 1176 diff.tv_usec / 1000; 1177 kpause(ttclos, false, uimax(mstohz(ms), 1), 1178 &sc->sc_lock); 1179 microuptime(&now); 1180 } 1181 timerclear(&sc->sc_hup_pending); 1182 } 1183 1184 /* Turn on interrupts. */ 1185 sc->sc_ier = IER_ERXRDY | IER_ERLS; 1186 if (!ISSET(tp->t_cflag, CLOCAL)) 1187 sc->sc_ier |= IER_EMSC; 1188 1189 if (sc->sc_type == COM_TYPE_PXA2x0) 1190 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 1191 else if (sc->sc_type == COM_TYPE_INGENIC || 1192 sc->sc_type == COM_TYPE_TEGRA) 1193 sc->sc_ier |= IER_ERXTOUT; 1194 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1195 1196 /* Fetch the current modem control status, needed later. */ 1197 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 1198 1199 /* Clear PPS capture state on first open. */ 1200 mutex_spin_enter(&timecounter_lock); 1201 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 1202 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1203 pps_init(&sc->sc_pps_state); 1204 mutex_spin_exit(&timecounter_lock); 1205 1206 com_mutex_exit(sc); 1207 1208 /* 1209 * Initialize the termios status to the defaults. Add in the 1210 * sticky bits from TIOCSFLAGS. 1211 */ 1212 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1213 t.c_ospeed = comcons_info.rate; 1214 t.c_cflag = comcons_info.cflag; 1215 } else { 1216 t.c_ospeed = TTYDEF_SPEED; 1217 t.c_cflag = TTYDEF_CFLAG; 1218 } 1219 t.c_ispeed = t.c_ospeed; 1220 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1221 SET(t.c_cflag, CLOCAL); 1222 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1223 SET(t.c_cflag, CRTSCTS); 1224 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1225 SET(t.c_cflag, MDMBUF); 1226 /* Make sure comparam() will do something. */ 1227 tp->t_ospeed = 0; 1228 (void) comparam(tp, &t); 1229 tp->t_iflag = TTYDEF_IFLAG; 1230 tp->t_oflag = TTYDEF_OFLAG; 1231 tp->t_lflag = TTYDEF_LFLAG; 1232 ttychars(tp); 1233 ttsetwater(tp); 1234 1235 com_mutex_enter(sc); 1236 1237 /* 1238 * Turn on DTR. We must always do this, even if carrier is not 1239 * present, because otherwise we'd have to use TIOCSDTR 1240 * immediately after setting CLOCAL, which applications do not 1241 * expect. We always assert DTR while the device is open 1242 * unless explicitly requested to deassert it. 1243 */ 1244 com_modem(sc, 1); 1245 1246 /* Clear the input ring, and unblock. */ 1247 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1248 sc->sc_rbavail = com_rbuf_size; 1249 com_iflush(sc); 1250 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1251 com_hwiflow(sc); 1252 1253 #ifdef COM_DEBUG 1254 if (com_debug) 1255 comstatus(sc, "comopen "); 1256 #endif 1257 1258 com_mutex_exit(sc); 1259 } 1260 1261 splx(s); 1262 1263 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1264 if (error) 1265 goto bad; 1266 1267 error = (*tp->t_linesw->l_open)(dev, tp); 1268 if (error) 1269 goto bad; 1270 1271 return (0); 1272 1273 bad: 1274 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1275 /* 1276 * We failed to open the device, and nobody else had it opened. 1277 * Clean up the state as appropriate. 1278 */ 1279 com_shutdown(sc); 1280 } 1281 1282 return (error); 1283 } 1284 1285 int 1286 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1287 { 1288 struct com_softc *sc = 1289 device_lookup_private(&com_cd, COMUNIT(dev)); 1290 struct tty *tp = sc->sc_tty; 1291 1292 /* XXX This is for cons.c. */ 1293 if (!ISSET(tp->t_state, TS_ISOPEN)) 1294 return (0); 1295 /* 1296 * If the device is exclusively for kernel use, deny userland 1297 * close. 1298 */ 1299 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1300 return (0); 1301 1302 (*tp->t_linesw->l_close)(tp, flag); 1303 ttyclose(tp); 1304 1305 if (COM_ISALIVE(sc) == 0) 1306 return (0); 1307 1308 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1309 /* 1310 * Although we got a last close, the device may still be in 1311 * use; e.g. if this was the dialout node, and there are still 1312 * processes waiting for carrier on the non-dialout node. 1313 */ 1314 com_shutdown(sc); 1315 } 1316 1317 return (0); 1318 } 1319 1320 int 1321 comread(dev_t dev, struct uio *uio, int flag) 1322 { 1323 struct com_softc *sc = 1324 device_lookup_private(&com_cd, COMUNIT(dev)); 1325 struct tty *tp = sc->sc_tty; 1326 1327 if (COM_ISALIVE(sc) == 0) 1328 return (EIO); 1329 1330 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1331 } 1332 1333 int 1334 comwrite(dev_t dev, struct uio *uio, int flag) 1335 { 1336 struct com_softc *sc = 1337 device_lookup_private(&com_cd, COMUNIT(dev)); 1338 struct tty *tp = sc->sc_tty; 1339 1340 if (COM_ISALIVE(sc) == 0) 1341 return (EIO); 1342 1343 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1344 } 1345 1346 int 1347 compoll(dev_t dev, int events, struct lwp *l) 1348 { 1349 struct com_softc *sc = 1350 device_lookup_private(&com_cd, COMUNIT(dev)); 1351 struct tty *tp = sc->sc_tty; 1352 1353 if (COM_ISALIVE(sc) == 0) 1354 return (POLLHUP); 1355 1356 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1357 } 1358 1359 struct tty * 1360 comtty(dev_t dev) 1361 { 1362 struct com_softc *sc = 1363 device_lookup_private(&com_cd, COMUNIT(dev)); 1364 struct tty *tp = sc->sc_tty; 1365 1366 return (tp); 1367 } 1368 1369 int 1370 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1371 { 1372 struct com_softc *sc; 1373 struct tty *tp; 1374 int error; 1375 1376 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1377 if (sc == NULL) 1378 return ENXIO; 1379 if (COM_ISALIVE(sc) == 0) 1380 return (EIO); 1381 1382 tp = sc->sc_tty; 1383 1384 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1385 if (error != EPASSTHROUGH) 1386 return (error); 1387 1388 error = ttioctl(tp, cmd, data, flag, l); 1389 if (error != EPASSTHROUGH) 1390 return (error); 1391 1392 error = 0; 1393 switch (cmd) { 1394 case TIOCSFLAGS: 1395 error = kauth_authorize_device_tty(l->l_cred, 1396 KAUTH_DEVICE_TTY_PRIVSET, tp); 1397 break; 1398 default: 1399 /* nothing */ 1400 break; 1401 } 1402 if (error) { 1403 return error; 1404 } 1405 1406 com_mutex_enter(sc); 1407 1408 switch (cmd) { 1409 case TIOCSBRK: 1410 com_break(sc, 1); 1411 break; 1412 1413 case TIOCCBRK: 1414 com_break(sc, 0); 1415 break; 1416 1417 case TIOCSDTR: 1418 com_modem(sc, 1); 1419 break; 1420 1421 case TIOCCDTR: 1422 com_modem(sc, 0); 1423 break; 1424 1425 case TIOCGFLAGS: 1426 *(int *)data = sc->sc_swflags; 1427 break; 1428 1429 case TIOCSFLAGS: 1430 sc->sc_swflags = *(int *)data; 1431 break; 1432 1433 case TIOCMSET: 1434 case TIOCMBIS: 1435 case TIOCMBIC: 1436 tiocm_to_com(sc, cmd, *(int *)data); 1437 break; 1438 1439 case TIOCMGET: 1440 *(int *)data = com_to_tiocm(sc); 1441 break; 1442 1443 case PPS_IOC_CREATE: 1444 case PPS_IOC_DESTROY: 1445 case PPS_IOC_GETPARAMS: 1446 case PPS_IOC_SETPARAMS: 1447 case PPS_IOC_GETCAP: 1448 case PPS_IOC_FETCH: 1449 #ifdef PPS_SYNC 1450 case PPS_IOC_KCBIND: 1451 #endif 1452 mutex_spin_enter(&timecounter_lock); 1453 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1454 mutex_spin_exit(&timecounter_lock); 1455 break; 1456 1457 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1458 mutex_spin_enter(&timecounter_lock); 1459 #ifndef PPS_TRAILING_EDGE 1460 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1461 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1462 #else 1463 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1464 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1465 #endif 1466 mutex_spin_exit(&timecounter_lock); 1467 break; 1468 1469 default: 1470 error = EPASSTHROUGH; 1471 break; 1472 } 1473 1474 com_mutex_exit(sc); 1475 1476 #ifdef COM_DEBUG 1477 if (com_debug) 1478 comstatus(sc, "comioctl "); 1479 #endif 1480 1481 return (error); 1482 } 1483 1484 static inline void 1485 com_schedrx(struct com_softc *sc) 1486 { 1487 sc->sc_rx_ready = 1; 1488 1489 /* Wake up the poller. */ 1490 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 1491 workqueue_enqueue(sc->sc_wq,(struct work *)&sc->sc_wk,NULL); 1492 else 1493 softint_schedule(sc->sc_si); 1494 } 1495 1496 void 1497 com_break(struct com_softc *sc, int onoff) 1498 { 1499 1500 if (onoff) 1501 SET(sc->sc_lcr, LCR_SBREAK); 1502 else 1503 CLR(sc->sc_lcr, LCR_SBREAK); 1504 1505 if (!sc->sc_heldchange) { 1506 if (sc->sc_tx_busy) { 1507 sc->sc_heldtbc = sc->sc_tbc; 1508 sc->sc_tbc = 0; 1509 sc->sc_heldchange = 1; 1510 } else 1511 com_loadchannelregs(sc); 1512 } 1513 } 1514 1515 void 1516 com_modem(struct com_softc *sc, int onoff) 1517 { 1518 1519 if (sc->sc_mcr_dtr == 0) 1520 return; 1521 1522 if (onoff) 1523 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1524 else 1525 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1526 1527 if (!sc->sc_heldchange) { 1528 if (sc->sc_tx_busy) { 1529 sc->sc_heldtbc = sc->sc_tbc; 1530 sc->sc_tbc = 0; 1531 sc->sc_heldchange = 1; 1532 } else 1533 com_loadchannelregs(sc); 1534 } 1535 } 1536 1537 void 1538 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1539 { 1540 u_char combits; 1541 1542 combits = 0; 1543 if (ISSET(ttybits, TIOCM_DTR)) 1544 SET(combits, MCR_DTR); 1545 if (ISSET(ttybits, TIOCM_RTS)) 1546 SET(combits, MCR_RTS); 1547 1548 switch (how) { 1549 case TIOCMBIC: 1550 CLR(sc->sc_mcr, combits); 1551 break; 1552 1553 case TIOCMBIS: 1554 SET(sc->sc_mcr, combits); 1555 break; 1556 1557 case TIOCMSET: 1558 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1559 SET(sc->sc_mcr, combits); 1560 break; 1561 } 1562 1563 if (!sc->sc_heldchange) { 1564 if (sc->sc_tx_busy) { 1565 sc->sc_heldtbc = sc->sc_tbc; 1566 sc->sc_tbc = 0; 1567 sc->sc_heldchange = 1; 1568 } else 1569 com_loadchannelregs(sc); 1570 } 1571 } 1572 1573 int 1574 com_to_tiocm(struct com_softc *sc) 1575 { 1576 u_char combits; 1577 int ttybits = 0; 1578 1579 combits = sc->sc_mcr; 1580 if (ISSET(combits, MCR_DTR)) 1581 SET(ttybits, TIOCM_DTR); 1582 if (ISSET(combits, MCR_RTS)) 1583 SET(ttybits, TIOCM_RTS); 1584 1585 combits = sc->sc_msr; 1586 if (sc->sc_type == COM_TYPE_INGENIC) { 1587 SET(ttybits, TIOCM_CD); 1588 } else { 1589 if (ISSET(combits, MSR_DCD)) 1590 SET(ttybits, TIOCM_CD); 1591 } 1592 if (ISSET(combits, MSR_CTS)) 1593 SET(ttybits, TIOCM_CTS); 1594 if (ISSET(combits, MSR_DSR)) 1595 SET(ttybits, TIOCM_DSR); 1596 if (ISSET(combits, MSR_RI | MSR_TERI)) 1597 SET(ttybits, TIOCM_RI); 1598 1599 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1600 SET(ttybits, TIOCM_LE); 1601 1602 return (ttybits); 1603 } 1604 1605 static u_char 1606 cflag2lcr(tcflag_t cflag) 1607 { 1608 u_char lcr = 0; 1609 1610 switch (ISSET(cflag, CSIZE)) { 1611 case CS5: 1612 SET(lcr, LCR_5BITS); 1613 break; 1614 case CS6: 1615 SET(lcr, LCR_6BITS); 1616 break; 1617 case CS7: 1618 SET(lcr, LCR_7BITS); 1619 break; 1620 case CS8: 1621 SET(lcr, LCR_8BITS); 1622 break; 1623 } 1624 if (ISSET(cflag, PARENB)) { 1625 SET(lcr, LCR_PENAB); 1626 if (!ISSET(cflag, PARODD)) 1627 SET(lcr, LCR_PEVEN); 1628 } 1629 if (ISSET(cflag, CSTOPB)) 1630 SET(lcr, LCR_STOPB); 1631 1632 return (lcr); 1633 } 1634 1635 int 1636 comparam(struct tty *tp, struct termios *t) 1637 { 1638 struct com_softc *sc = 1639 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1640 int ospeed; 1641 u_char lcr; 1642 1643 if (COM_ISALIVE(sc) == 0) 1644 return (EIO); 1645 1646 if (sc->sc_type == COM_TYPE_HAYESP) { 1647 int prescaler, speed; 1648 1649 /* 1650 * Calculate UART clock prescaler. It should be in 1651 * range of 0 .. 3. 1652 */ 1653 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1654 prescaler++, speed /= 2) 1655 if ((ospeed = comspeed(speed, sc->sc_frequency, 1656 sc->sc_type)) > 0) 1657 break; 1658 1659 if (prescaler == 4) 1660 return (EINVAL); 1661 sc->sc_prescaler = prescaler; 1662 } else { 1663 if (ISSET(sc->sc_hwflags, COM_HW_MCRPRESCALE)) { 1664 /* Try it without the prescaler, if that fails, enable 1665 * the prescaler and try again. 1666 */ 1667 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1668 CLR(sc->sc_mcr, MCR_PRESCALE); 1669 if (ospeed < 0) { 1670 ospeed = comspeed(t->c_ospeed, sc->sc_frequency / 4, sc->sc_type); 1671 if (ospeed >= 0) 1672 SET(sc->sc_mcr, MCR_PRESCALE); 1673 } 1674 } else { 1675 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1676 } 1677 } 1678 1679 /* Check requested parameters. */ 1680 if (ospeed < 0) 1681 return (EINVAL); 1682 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1683 return (EINVAL); 1684 1685 /* 1686 * For the console, always force CLOCAL and !HUPCL, so that the port 1687 * is always active. 1688 */ 1689 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1690 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1691 SET(t->c_cflag, CLOCAL); 1692 CLR(t->c_cflag, HUPCL); 1693 } 1694 1695 /* 1696 * If there were no changes, don't do anything. This avoids dropping 1697 * input and improves performance when all we did was frob things like 1698 * VMIN and VTIME. 1699 */ 1700 if (tp->t_ospeed == t->c_ospeed && 1701 tp->t_cflag == t->c_cflag) 1702 return (0); 1703 1704 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1705 1706 com_mutex_enter(sc); 1707 1708 sc->sc_lcr = lcr; 1709 1710 /* 1711 * If we're not in a mode that assumes a connection is present, then 1712 * ignore carrier changes. 1713 */ 1714 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1715 sc->sc_msr_dcd = 0; 1716 else 1717 sc->sc_msr_dcd = MSR_DCD; 1718 /* 1719 * Set the flow control pins depending on the current flow control 1720 * mode. 1721 */ 1722 if (ISSET(t->c_cflag, CRTSCTS)) { 1723 sc->sc_mcr_dtr = MCR_DTR; 1724 sc->sc_mcr_rts = MCR_RTS; 1725 sc->sc_msr_cts = MSR_CTS; 1726 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1727 SET(sc->sc_mcr, MCR_AFE); 1728 } else { 1729 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1730 } 1731 } else if (ISSET(t->c_cflag, MDMBUF)) { 1732 /* 1733 * For DTR/DCD flow control, make sure we don't toggle DTR for 1734 * carrier detection. 1735 */ 1736 sc->sc_mcr_dtr = 0; 1737 sc->sc_mcr_rts = MCR_DTR; 1738 sc->sc_msr_cts = MSR_DCD; 1739 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1740 CLR(sc->sc_mcr, MCR_AFE); 1741 } else { 1742 sc->sc_efr = 0; 1743 } 1744 } else { 1745 /* 1746 * If no flow control, then always set RTS. This will make 1747 * the other side happy if it mistakenly thinks we're doing 1748 * RTS/CTS flow control. 1749 */ 1750 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1751 sc->sc_mcr_rts = 0; 1752 sc->sc_msr_cts = 0; 1753 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1754 CLR(sc->sc_mcr, MCR_AFE); 1755 } else { 1756 sc->sc_efr = 0; 1757 } 1758 if (ISSET(sc->sc_mcr, MCR_DTR)) 1759 SET(sc->sc_mcr, MCR_RTS); 1760 else 1761 CLR(sc->sc_mcr, MCR_RTS); 1762 } 1763 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1764 1765 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1766 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1767 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1768 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1769 1770 sc->sc_dlbl = ospeed; 1771 sc->sc_dlbh = ospeed >> 8; 1772 1773 /* 1774 * Set the FIFO threshold based on the receive speed. 1775 * 1776 * * If it's a low speed, it's probably a mouse or some other 1777 * interactive device, so set the threshold low. 1778 * * If it's a high speed, trim the trigger level down to prevent 1779 * overflows. 1780 * * Otherwise set it a bit higher. 1781 */ 1782 if (sc->sc_type == COM_TYPE_HAYESP) { 1783 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1784 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1785 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1786 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1787 if (t->c_ospeed <= 1200) 1788 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1789 else if (t->c_ospeed <= 38400) 1790 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1791 else 1792 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1793 } else { 1794 sc->sc_fifo = 0; 1795 } 1796 1797 if (sc->sc_type == COM_TYPE_INGENIC) 1798 sc->sc_fifo |= FIFO_UART_ON; 1799 1800 /* And copy to tty. */ 1801 tp->t_ispeed = t->c_ospeed; 1802 tp->t_ospeed = t->c_ospeed; 1803 tp->t_cflag = t->c_cflag; 1804 1805 if (!sc->sc_heldchange) { 1806 if (sc->sc_tx_busy) { 1807 sc->sc_heldtbc = sc->sc_tbc; 1808 sc->sc_tbc = 0; 1809 sc->sc_heldchange = 1; 1810 } else 1811 com_loadchannelregs(sc); 1812 } 1813 1814 if (!ISSET(t->c_cflag, CHWFLOW)) { 1815 /* Disable the high water mark. */ 1816 sc->sc_r_hiwat = 0; 1817 sc->sc_r_lowat = 0; 1818 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1819 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1820 com_schedrx(sc); 1821 } 1822 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1823 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1824 com_hwiflow(sc); 1825 } 1826 } else { 1827 sc->sc_r_hiwat = com_rbuf_hiwat; 1828 sc->sc_r_lowat = com_rbuf_lowat; 1829 } 1830 1831 com_mutex_exit(sc); 1832 1833 /* 1834 * Update the tty layer's idea of the carrier bit, in case we changed 1835 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1836 * explicit request. 1837 */ 1838 if (sc->sc_type == COM_TYPE_INGENIC) { 1839 /* no DCD here */ 1840 (void) (*tp->t_linesw->l_modem)(tp, 1); 1841 } else 1842 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1843 1844 #ifdef COM_DEBUG 1845 if (com_debug) 1846 comstatus(sc, "comparam "); 1847 #endif 1848 1849 if (!ISSET(t->c_cflag, CHWFLOW)) { 1850 if (sc->sc_tx_stopped) { 1851 sc->sc_tx_stopped = 0; 1852 comstart(tp); 1853 } 1854 } 1855 1856 return (0); 1857 } 1858 1859 void 1860 com_iflush(struct com_softc *sc) 1861 { 1862 struct com_regs *regsp = &sc->sc_regs; 1863 uint8_t fifo; 1864 #ifdef DIAGNOSTIC 1865 int reg; 1866 #endif 1867 int timo; 1868 1869 #ifdef DIAGNOSTIC 1870 reg = 0xffff; 1871 #endif 1872 timo = 50000; 1873 /* flush any pending I/O */ 1874 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1875 && --timo) 1876 #ifdef DIAGNOSTIC 1877 reg = 1878 #else 1879 (void) 1880 #endif 1881 CSR_READ_1(regsp, COM_REG_RXDATA); 1882 #ifdef DIAGNOSTIC 1883 if (!timo) 1884 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1885 #endif 1886 1887 switch (sc->sc_type) { 1888 case COM_TYPE_16750: 1889 case COM_TYPE_DW_APB: 1890 /* 1891 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1892 * This should prevent triggering busy interrupt while 1893 * manipulating divisors. 1894 */ 1895 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1896 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1897 CSR_WRITE_1(regsp, COM_REG_FIFO, 1898 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1899 delay(100); 1900 break; 1901 } 1902 } 1903 1904 void 1905 com_loadchannelregs(struct com_softc *sc) 1906 { 1907 struct com_regs *regsp = &sc->sc_regs; 1908 1909 /* XXXXX necessary? */ 1910 com_iflush(sc); 1911 1912 if (sc->sc_type == COM_TYPE_PXA2x0) 1913 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1914 else 1915 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1916 1917 if (sc->sc_type == COM_TYPE_OMAP) { 1918 /* disable before changing settings */ 1919 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1920 } 1921 1922 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1923 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1924 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1925 /* no EFR on alchemy */ 1926 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1927 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1928 } 1929 if (ISSET(sc->sc_hwflags, COM_HW_MCRPRESCALE)) { 1930 /* Unlock the prescale bit */ 1931 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1932 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr | EFR_EFCR); 1933 } 1934 if (sc->sc_type == COM_TYPE_AU1x00) { 1935 /* alchemy has single separate 16-bit clock divisor register */ 1936 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1937 (sc->sc_dlbh << 8)); 1938 } else { 1939 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1940 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1941 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1942 } 1943 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1944 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1945 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1946 if (ISSET(sc->sc_hwflags, COM_HW_MCRPRESCALE)) { 1947 /* Lock the prescale bit back up again */ 1948 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1949 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1950 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1951 } 1952 if (sc->sc_type == COM_TYPE_HAYESP) { 1953 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1954 HAYESP_SETPRESCALER); 1955 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1956 sc->sc_prescaler); 1957 } 1958 if (sc->sc_type == COM_TYPE_OMAP) { 1959 /* setup the fifos. the FCR value is not used as long 1960 as SCR[6] and SCR[7] are 0, which they are at reset 1961 and we never touch the SCR register */ 1962 uint8_t rx_fifo_trig = 40; 1963 uint8_t tx_fifo_trig = 60; 1964 uint8_t rx_start = 8; 1965 uint8_t rx_halt = 60; 1966 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1967 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1968 1969 /* enable access to TCR & TLR */ 1970 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1971 1972 /* write tcr and tlr values */ 1973 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1974 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1975 1976 /* disable access to TCR & TLR */ 1977 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1978 1979 /* enable again, but mode is based on speed */ 1980 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1981 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1982 } else { 1983 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1984 } 1985 } 1986 1987 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1988 } 1989 1990 int 1991 comhwiflow(struct tty *tp, int block) 1992 { 1993 struct com_softc *sc = 1994 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1995 1996 if (COM_ISALIVE(sc) == 0) 1997 return (0); 1998 1999 if (sc->sc_mcr_rts == 0) 2000 return (0); 2001 2002 com_mutex_enter(sc); 2003 2004 if (block) { 2005 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 2006 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 2007 com_hwiflow(sc); 2008 } 2009 } else { 2010 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 2011 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 2012 com_schedrx(sc); 2013 } 2014 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 2015 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 2016 com_hwiflow(sc); 2017 } 2018 } 2019 2020 com_mutex_exit(sc); 2021 return (1); 2022 } 2023 2024 int 2025 comhwiflowsoft(struct tty *tp, int block) 2026 { 2027 int r; 2028 2029 mutex_spin_exit(&tty_lock); 2030 r = comhwiflow(tp, block); 2031 mutex_spin_enter(&tty_lock); 2032 2033 return r; 2034 } 2035 2036 /* 2037 * (un)block input via hw flowcontrol 2038 */ 2039 void 2040 com_hwiflow(struct com_softc *sc) 2041 { 2042 struct com_regs *regsp= &sc->sc_regs; 2043 2044 if (sc->sc_mcr_rts == 0) 2045 return; 2046 2047 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 2048 CLR(sc->sc_mcr, sc->sc_mcr_rts); 2049 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 2050 } else { 2051 SET(sc->sc_mcr, sc->sc_mcr_rts); 2052 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 2053 } 2054 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 2055 } 2056 2057 2058 void 2059 comstart(struct tty *tp) 2060 { 2061 struct com_softc *sc = 2062 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 2063 struct com_regs *regsp = &sc->sc_regs; 2064 2065 if (COM_ISALIVE(sc) == 0) 2066 return; 2067 2068 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 2069 return; 2070 if (sc->sc_tx_stopped) 2071 return; 2072 if (!ttypull(tp)) 2073 return; 2074 2075 /* Grab the first contiguous region of buffer space. */ 2076 { 2077 u_char *tba; 2078 int tbc; 2079 2080 tba = tp->t_outq.c_cf; 2081 tbc = ndqb(&tp->t_outq, 0); 2082 2083 com_mutex_enter(sc); 2084 2085 sc->sc_tba = tba; 2086 sc->sc_tbc = tbc; 2087 } 2088 2089 SET(tp->t_state, TS_BUSY); 2090 sc->sc_tx_busy = 1; 2091 2092 /* Enable transmit completion interrupts if necessary. */ 2093 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 2094 SET(sc->sc_ier, IER_ETXRDY); 2095 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2096 } 2097 2098 /* Output the first chunk of the contiguous buffer. */ 2099 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 2100 u_int n; 2101 2102 n = sc->sc_tbc; 2103 if (n > sc->sc_fifolen) 2104 n = sc->sc_fifolen; 2105 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2106 sc->sc_tbc -= n; 2107 sc->sc_tba += n; 2108 } 2109 2110 com_mutex_exit(sc); 2111 } 2112 2113 /* Do an ugly thing in the softirq case. We can't have a spin lock held right now, 2114 * so drop it. 2115 */ 2116 2117 void 2118 comstartsoft(struct tty *tp) 2119 { 2120 mutex_spin_exit(&tty_lock); 2121 comstart(tp); 2122 mutex_spin_enter(&tty_lock); 2123 } 2124 2125 /* 2126 * Stop output on a line. 2127 * 2128 * For reasons that are not obvious dropping the tty_lock spin lock was not 2129 * enough for the stop call and if you try to acquire a adaptive lock while 2130 * holding a spin lock you will panic, so just don't acquire it. 2131 */ 2132 void 2133 comstop(struct tty *tp, int flag) 2134 { 2135 struct com_softc *sc = 2136 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 2137 2138 if (!ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 2139 com_mutex_enter(sc); 2140 if (ISSET(tp->t_state, TS_BUSY)) { 2141 /* Stop transmitting at the next chunk. */ 2142 sc->sc_tbc = 0; 2143 sc->sc_heldtbc = 0; 2144 if (!ISSET(tp->t_state, TS_TTSTOP)) 2145 SET(tp->t_state, TS_FLUSH); 2146 } 2147 if (!ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 2148 com_mutex_exit(sc); 2149 } 2150 2151 2152 void 2153 comdiag(void *arg) 2154 { 2155 struct com_softc *sc = arg; 2156 int overflows, floods; 2157 2158 com_mutex_enter(sc); 2159 overflows = sc->sc_overflows; 2160 sc->sc_overflows = 0; 2161 floods = sc->sc_floods; 2162 sc->sc_floods = 0; 2163 sc->sc_errors = 0; 2164 com_mutex_exit(sc); 2165 2166 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 2167 device_xname(sc->sc_dev), 2168 overflows, overflows == 1 ? "" : "s", 2169 floods, floods == 1 ? "" : "s"); 2170 } 2171 2172 static inline void 2173 com_rxsoft(struct com_softc *sc, struct tty *tp) 2174 { 2175 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 2176 u_char *get, *end; 2177 u_int cc, scc; 2178 u_char lsr; 2179 int code; 2180 2181 end = sc->sc_ebuf; 2182 get = sc->sc_rbget; 2183 scc = cc = com_rbuf_size - sc->sc_rbavail; 2184 2185 if (cc == com_rbuf_size) { 2186 sc->sc_floods++; 2187 if (sc->sc_errors++ == 0) 2188 callout_reset(&sc->sc_diag_callout, 60 * hz, 2189 comdiag, sc); 2190 } 2191 2192 /* If not yet open, drop the entire buffer content here */ 2193 if (!ISSET(tp->t_state, TS_ISOPEN)) { 2194 get += cc << 1; 2195 if (get >= end) 2196 get -= com_rbuf_size << 1; 2197 cc = 0; 2198 } 2199 while (cc) { 2200 code = get[0]; 2201 lsr = get[1]; 2202 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 2203 if (ISSET(lsr, LSR_OE)) { 2204 sc->sc_overflows++; 2205 if (sc->sc_errors++ == 0) 2206 callout_reset(&sc->sc_diag_callout, 2207 60 * hz, comdiag, sc); 2208 } 2209 if (ISSET(lsr, LSR_BI | LSR_FE)) 2210 SET(code, TTY_FE); 2211 if (ISSET(lsr, LSR_PE)) 2212 SET(code, TTY_PE); 2213 } 2214 if ((*rint)(code, tp) == -1) { 2215 /* 2216 * The line discipline's buffer is out of space. 2217 */ 2218 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 2219 /* 2220 * We're either not using flow control, or the 2221 * line discipline didn't tell us to block for 2222 * some reason. Either way, we have no way to 2223 * know when there's more space available, so 2224 * just drop the rest of the data. 2225 */ 2226 get += cc << 1; 2227 if (get >= end) 2228 get -= com_rbuf_size << 1; 2229 cc = 0; 2230 } else { 2231 /* 2232 * Don't schedule any more receive processing 2233 * until the line discipline tells us there's 2234 * space available (through comhwiflow()). 2235 * Leave the rest of the data in the input 2236 * buffer. 2237 */ 2238 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 2239 } 2240 break; 2241 } 2242 get += 2; 2243 if (get >= end) 2244 get = sc->sc_rbuf; 2245 cc--; 2246 } 2247 2248 if (cc != scc) { 2249 sc->sc_rbget = get; 2250 com_mutex_enter(sc); 2251 2252 cc = sc->sc_rbavail += scc - cc; 2253 /* Buffers should be ok again, release possible block. */ 2254 if (cc >= sc->sc_r_lowat) { 2255 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2256 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2257 SET(sc->sc_ier, IER_ERXRDY); 2258 if (sc->sc_type == COM_TYPE_PXA2x0) 2259 SET(sc->sc_ier, IER_ERXTOUT); 2260 if (sc->sc_type == COM_TYPE_INGENIC || 2261 sc->sc_type == COM_TYPE_TEGRA) 2262 SET(sc->sc_ier, IER_ERXTOUT); 2263 2264 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 2265 sc->sc_ier); 2266 } 2267 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 2268 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2269 com_hwiflow(sc); 2270 } 2271 } 2272 com_mutex_exit(sc); 2273 } 2274 } 2275 2276 static inline void 2277 com_txsoft(struct com_softc *sc, struct tty *tp) 2278 { 2279 2280 CLR(tp->t_state, TS_BUSY); 2281 if (ISSET(tp->t_state, TS_FLUSH)) 2282 CLR(tp->t_state, TS_FLUSH); 2283 else 2284 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2285 2286 /* This used to be (*tp->t_linesw->l_start)(tp) which is probably more 2287 * correct, however... in the softirq case, it won't work as comstartsoft 2288 * will try and drop the spin lock and there isn't one of those when called 2289 * from here. In any case, l_start is just comstartsoft or comstart anyway 2290 * and there are other places in this code that just calls comstart, so 2291 * do likewise. 2292 */ 2293 comstart(tp); 2294 } 2295 2296 static inline void 2297 com_stsoft(struct com_softc *sc, struct tty *tp) 2298 { 2299 u_char msr, delta; 2300 2301 com_mutex_enter(sc); 2302 msr = sc->sc_msr; 2303 delta = sc->sc_msr_delta; 2304 sc->sc_msr_delta = 0; 2305 com_mutex_exit(sc); 2306 2307 if (ISSET(delta, sc->sc_msr_dcd)) { 2308 /* 2309 * Inform the tty layer that carrier detect changed. 2310 */ 2311 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2312 } 2313 2314 if (ISSET(delta, sc->sc_msr_cts)) { 2315 /* Block or unblock output according to flow control. */ 2316 if (ISSET(msr, sc->sc_msr_cts)) { 2317 sc->sc_tx_stopped = 0; 2318 /* See note above about (*tp->t_linesw->l_start)(tp); */ 2319 comstart(tp); 2320 } else { 2321 sc->sc_tx_stopped = 1; 2322 } 2323 } 2324 2325 #ifdef COM_DEBUG 2326 if (com_debug) 2327 comstatus(sc, "com_stsoft"); 2328 #endif 2329 } 2330 2331 void 2332 comsoft(void *arg) 2333 { 2334 struct com_softc *sc = arg; 2335 struct tty *tp; 2336 2337 if (COM_ISALIVE(sc) == 0) 2338 return; 2339 2340 tp = sc->sc_tty; 2341 2342 if (sc->sc_rx_ready) { 2343 sc->sc_rx_ready = 0; 2344 com_rxsoft(sc, tp); 2345 } 2346 2347 if (sc->sc_st_check) { 2348 sc->sc_st_check = 0; 2349 com_stsoft(sc, tp); 2350 } 2351 2352 if (sc->sc_tx_done) { 2353 sc->sc_tx_done = 0; 2354 com_txsoft(sc, tp); 2355 } 2356 } 2357 2358 static void 2359 comsoftwq(struct work *wk, void *arg) 2360 { 2361 struct com_softc *sc = arg; 2362 2363 comsoft(sc); 2364 } 2365 2366 int 2367 comintr(void *arg) 2368 { 2369 struct com_softc *sc = arg; 2370 struct com_regs *regsp = &sc->sc_regs; 2371 2372 u_char *put, *end; 2373 u_int cc; 2374 u_char lsr, iir; 2375 2376 if (COM_ISALIVE(sc) == 0) 2377 return (0); 2378 2379 KASSERT(regsp != NULL); 2380 2381 com_mutex_enter(sc); 2382 iir = CSR_READ_1(regsp, COM_REG_IIR); 2383 2384 /* Handle ns16750-specific busy interrupt. */ 2385 if (sc->sc_type == COM_TYPE_16750 && 2386 (iir & IIR_BUSY) == IIR_BUSY) { 2387 for (int timeout = 10000; 2388 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2389 if (timeout <= 0) { 2390 aprint_error_dev(sc->sc_dev, 2391 "timeout while waiting for BUSY interrupt " 2392 "acknowledge\n"); 2393 com_mutex_exit(sc); 2394 return (0); 2395 } 2396 2397 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2398 iir = CSR_READ_1(regsp, COM_REG_IIR); 2399 } 2400 2401 /* DesignWare APB UART BUSY interrupt */ 2402 if (sc->sc_type == COM_TYPE_DW_APB && 2403 (iir & IIR_BUSY) == IIR_BUSY) { 2404 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 2405 (void)CSR_READ_1(regsp, COM_REG_USR); 2406 } else if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2407 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2408 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2409 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2410 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2411 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2412 CSR_WRITE_1(regsp, COM_REG_HALT, 2413 HALT_CHCFG_EN | HALT_CHCFG_UD); 2414 for (int timeout = 10000000; 2415 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2416 timeout--) { 2417 if (timeout <= 0) { 2418 aprint_error_dev(sc->sc_dev, 2419 "timeout while waiting for HALT " 2420 "update acknowledge 0x%x 0x%x\n", 2421 CSR_READ_1(regsp, COM_REG_HALT), 2422 CSR_READ_1(regsp, COM_REG_USR)); 2423 break; 2424 } 2425 } 2426 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2427 (void)CSR_READ_1(regsp, COM_REG_USR); 2428 } else { 2429 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2430 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2431 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2432 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2433 } 2434 } 2435 2436 end = sc->sc_ebuf; 2437 put = sc->sc_rbput; 2438 cc = sc->sc_rbavail; 2439 2440 if (ISSET(iir, IIR_NOPEND)) { 2441 if (ISSET(sc->sc_hwflags, COM_HW_BROKEN_ETXRDY)) 2442 goto do_tx; 2443 com_mutex_exit(sc); 2444 return (0); 2445 } 2446 2447 again: do { 2448 u_char msr, delta; 2449 2450 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2451 if (ISSET(lsr, LSR_BI)) { 2452 int cn_trapped = 0; /* see above: cn_trap() */ 2453 2454 cn_check_magic(sc->sc_tty->t_dev, 2455 CNC_BREAK, com_cnm_state); 2456 if (cn_trapped) 2457 continue; 2458 #if defined(KGDB) && !defined(DDB) 2459 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2460 kgdb_connect(1); 2461 continue; 2462 } 2463 #endif 2464 } 2465 2466 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2467 lsr |= LSR_RXRDY; 2468 2469 if (ISSET(lsr, LSR_RCV_MASK) && 2470 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2471 while (cc > 0) { 2472 int cn_trapped = 0; 2473 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2474 put[1] = lsr; 2475 cn_check_magic(sc->sc_tty->t_dev, 2476 put[0], com_cnm_state); 2477 if (cn_trapped) 2478 goto next; 2479 put += 2; 2480 if (put >= end) 2481 put = sc->sc_rbuf; 2482 cc--; 2483 next: 2484 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2485 if (!ISSET(lsr, LSR_RCV_MASK)) 2486 break; 2487 } 2488 2489 /* 2490 * Current string of incoming characters ended because 2491 * no more data was available or we ran out of space. 2492 * Schedule a receive event if any data was received. 2493 * If we're out of space, turn off receive interrupts. 2494 */ 2495 sc->sc_rbput = put; 2496 sc->sc_rbavail = cc; 2497 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2498 sc->sc_rx_ready = 1; 2499 2500 /* 2501 * See if we are in danger of overflowing a buffer. If 2502 * so, use hardware flow control to ease the pressure. 2503 */ 2504 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2505 cc < sc->sc_r_hiwat) { 2506 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2507 com_hwiflow(sc); 2508 } 2509 2510 /* 2511 * If we're out of space, disable receive interrupts 2512 * until the queue has drained a bit. 2513 */ 2514 if (!cc) { 2515 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2516 switch (sc->sc_type) { 2517 case COM_TYPE_PXA2x0: 2518 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2519 break; 2520 case COM_TYPE_INGENIC: 2521 case COM_TYPE_TEGRA: 2522 CLR(sc->sc_ier, 2523 IER_ERXRDY | IER_ERXTOUT); 2524 break; 2525 default: 2526 CLR(sc->sc_ier, IER_ERXRDY); 2527 break; 2528 } 2529 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2530 } 2531 } else { 2532 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2533 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2534 continue; 2535 } 2536 } 2537 2538 msr = CSR_READ_1(regsp, COM_REG_MSR); 2539 delta = msr ^ sc->sc_msr; 2540 sc->sc_msr = msr; 2541 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2542 (delta & MSR_DCD)) { 2543 mutex_spin_enter(&timecounter_lock); 2544 pps_capture(&sc->sc_pps_state); 2545 pps_event(&sc->sc_pps_state, 2546 (msr & MSR_DCD) ? 2547 PPS_CAPTUREASSERT : 2548 PPS_CAPTURECLEAR); 2549 mutex_spin_exit(&timecounter_lock); 2550 } 2551 2552 /* 2553 * Process normal status changes 2554 */ 2555 if (ISSET(delta, sc->sc_msr_mask)) { 2556 SET(sc->sc_msr_delta, delta); 2557 2558 /* 2559 * Stop output immediately if we lose the output 2560 * flow control signal or carrier detect. 2561 */ 2562 if (ISSET(~msr, sc->sc_msr_mask)) { 2563 sc->sc_tbc = 0; 2564 sc->sc_heldtbc = 0; 2565 #ifdef COM_DEBUG 2566 if (com_debug) 2567 comstatus(sc, "comintr "); 2568 #endif 2569 } 2570 2571 sc->sc_st_check = 1; 2572 } 2573 } while (!ISSET((iir = 2574 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2575 /* 2576 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2577 * by IIR read, so we can't do this way: `process all interrupts, 2578 * then do TX if possible'. 2579 */ 2580 (iir & IIR_IMASK) != IIR_TXRDY); 2581 2582 do_tx: 2583 /* 2584 * Read LSR again, since there may be an interrupt between 2585 * the last LSR read and IIR read above. 2586 */ 2587 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2588 2589 /* 2590 * See if data can be transmitted as well. 2591 * Schedule tx done event if no data left 2592 * and tty was marked busy. 2593 */ 2594 if (ISSET(lsr, LSR_TXRDY)) { 2595 /* 2596 * If we've delayed a parameter change, do it now, and restart 2597 * output. 2598 */ 2599 if (sc->sc_heldchange) { 2600 com_loadchannelregs(sc); 2601 sc->sc_heldchange = 0; 2602 sc->sc_tbc = sc->sc_heldtbc; 2603 sc->sc_heldtbc = 0; 2604 } 2605 2606 /* Output the next chunk of the contiguous buffer, if any. */ 2607 if (sc->sc_tbc > 0) { 2608 u_int n; 2609 2610 n = sc->sc_tbc; 2611 if (n > sc->sc_fifolen) 2612 n = sc->sc_fifolen; 2613 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2614 sc->sc_tbc -= n; 2615 sc->sc_tba += n; 2616 } else { 2617 /* Disable transmit completion interrupts if necessary. */ 2618 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2619 CLR(sc->sc_ier, IER_ETXRDY); 2620 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2621 } 2622 if (sc->sc_tx_busy) { 2623 sc->sc_tx_busy = 0; 2624 sc->sc_tx_done = 1; 2625 } 2626 } 2627 } 2628 2629 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2630 goto again; 2631 2632 com_mutex_exit(sc); 2633 2634 /* Wake up the poller. */ 2635 if ((sc->sc_rx_ready | sc->sc_st_check | sc->sc_tx_done) != 0) { 2636 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 2637 workqueue_enqueue(sc->sc_wq,(struct work *)&sc->sc_wk,NULL); 2638 else 2639 softint_schedule(sc->sc_si); 2640 } 2641 2642 #ifdef RND_COM 2643 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2644 #endif 2645 2646 return (1); 2647 } 2648 2649 /* 2650 * The following functions are polled getc and putc routines, shared 2651 * by the console and kgdb glue. 2652 * 2653 * The read-ahead code is so that you can detect pending in-band 2654 * cn_magic in polled mode while doing output rather than having to 2655 * wait until the kernel decides it needs input. 2656 */ 2657 2658 #define MAX_READAHEAD 20 2659 static int com_readahead[MAX_READAHEAD]; 2660 static int com_readaheadcount = 0; 2661 2662 int 2663 com_common_getc(dev_t dev, struct com_regs *regsp) 2664 { 2665 int s = splserial(); 2666 u_char stat, c; 2667 2668 /* got a character from reading things earlier */ 2669 if (com_readaheadcount > 0) { 2670 int i; 2671 2672 c = com_readahead[0]; 2673 for (i = 1; i < com_readaheadcount; i++) { 2674 com_readahead[i-1] = com_readahead[i]; 2675 } 2676 com_readaheadcount--; 2677 splx(s); 2678 return (c); 2679 } 2680 2681 /* don't block until a character becomes available */ 2682 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2683 splx(s); 2684 return -1; 2685 } 2686 2687 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2688 stat = CSR_READ_1(regsp, COM_REG_IIR); 2689 { 2690 int cn_trapped = 0; /* required by cn_trap, see above */ 2691 if (!db_active) 2692 cn_check_magic(dev, c, com_cnm_state); 2693 } 2694 splx(s); 2695 return (c); 2696 } 2697 2698 static void 2699 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead) 2700 { 2701 int s = splserial(); 2702 int cin, stat, timo; 2703 2704 if (with_readahead && com_readaheadcount < MAX_READAHEAD 2705 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2706 int cn_trapped = 0; 2707 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2708 stat = CSR_READ_1(regsp, COM_REG_IIR); 2709 cn_check_magic(dev, cin, com_cnm_state); 2710 com_readahead[com_readaheadcount++] = cin; 2711 } 2712 2713 /* wait for any pending transmission to finish */ 2714 timo = 150000; 2715 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2716 continue; 2717 2718 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2719 COM_BARRIER(regsp, BR | BW); 2720 2721 splx(s); 2722 } 2723 2724 /* 2725 * Initialize UART for use as console or KGDB line. 2726 */ 2727 int 2728 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2729 tcflag_t cflag) 2730 { 2731 2732 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2733 ®sp->cr_ioh)) 2734 return (ENOMEM); /* ??? */ 2735 2736 if (type == COM_TYPE_OMAP) { 2737 /* disable before changing settings */ 2738 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2739 } 2740 2741 rate = comspeed(rate, frequency, type); 2742 if (rate != -1) { 2743 if (type == COM_TYPE_AU1x00) { 2744 /* no EFR on alchemy */ 2745 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2746 } else { 2747 if ((type != COM_TYPE_16550_NOERS) && 2748 (type != COM_TYPE_INGENIC)) { 2749 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2750 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2751 } 2752 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2753 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2754 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2755 } 2756 } 2757 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2758 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2759 2760 if (type == COM_TYPE_INGENIC) { 2761 CSR_WRITE_1(regsp, COM_REG_FIFO, 2762 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2763 FIFO_TRIGGER_1 | FIFO_UART_ON); 2764 } else { 2765 CSR_WRITE_1(regsp, COM_REG_FIFO, 2766 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2767 FIFO_TRIGGER_1); 2768 } 2769 2770 if (type == COM_TYPE_OMAP) { 2771 /* setup the fifos. the FCR value is not used as long 2772 as SCR[6] and SCR[7] are 0, which they are at reset 2773 and we never touch the SCR register */ 2774 uint8_t rx_fifo_trig = 40; 2775 uint8_t tx_fifo_trig = 60; 2776 uint8_t rx_start = 8; 2777 uint8_t rx_halt = 60; 2778 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2779 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2780 2781 /* enable access to TCR & TLR */ 2782 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2783 2784 /* write tcr and tlr values */ 2785 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2786 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2787 2788 /* disable access to TCR & TLR */ 2789 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2790 2791 /* enable again, but mode is based on speed */ 2792 if (rate > 230400) { 2793 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2794 } else { 2795 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2796 } 2797 } 2798 2799 if (type == COM_TYPE_PXA2x0) 2800 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2801 else 2802 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2803 2804 return (0); 2805 } 2806 2807 int 2808 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2809 tcflag_t cflag) 2810 { 2811 int res; 2812 2813 comcons_info.regs = *regsp; 2814 2815 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2816 if (res) 2817 return (res); 2818 2819 cn_tab = &comcons; 2820 cn_init_magic(&com_cnm_state); 2821 cn_set_magic("\047\001"); /* default magic is BREAK */ 2822 2823 comcons_info.frequency = frequency; 2824 comcons_info.type = type; 2825 comcons_info.rate = rate; 2826 comcons_info.cflag = cflag; 2827 2828 return (0); 2829 } 2830 2831 int 2832 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2833 int type, tcflag_t cflag) 2834 { 2835 struct com_regs regs; 2836 2837 /*XXX*/ 2838 bus_space_handle_t dummy_bsh; 2839 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2840 2841 /* 2842 * dummy_bsh required because com_init_regs() wants it. A 2843 * real bus_space_handle will be filled in by cominit() later. 2844 * XXXJRT Detangle this mess eventually, plz. 2845 */ 2846 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2847 2848 return comcnattach1(®s, rate, frequency, type, cflag); 2849 } 2850 2851 static int 2852 comcnreattach(void) 2853 { 2854 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2855 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2856 } 2857 2858 int 2859 comcngetc(dev_t dev) 2860 { 2861 2862 return (com_common_getc(dev, &comcons_info.regs)); 2863 } 2864 2865 /* 2866 * Console kernel output character routine. 2867 */ 2868 void 2869 comcnputc(dev_t dev, int c) 2870 { 2871 2872 com_common_putc(dev, &comcons_info.regs, c, cold); 2873 } 2874 2875 void 2876 comcnpollc(dev_t dev, int on) 2877 { 2878 2879 com_readaheadcount = 0; 2880 } 2881 2882 #ifdef KGDB 2883 int 2884 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2885 tcflag_t cflag) 2886 { 2887 int res; 2888 2889 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2890 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2891 #if !defined(DDB) 2892 return (EBUSY); /* cannot share with console */ 2893 #else 2894 comkgdbregs = *regsp; 2895 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2896 #endif 2897 } else { 2898 comkgdbregs = *regsp; 2899 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2900 if (res) 2901 return (res); 2902 2903 /* 2904 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2905 * expects this to be initialized 2906 */ 2907 cn_init_magic(&com_cnm_state); 2908 cn_set_magic("\047\001"); 2909 } 2910 2911 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2912 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2913 2914 return (0); 2915 } 2916 2917 int 2918 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2919 int frequency, int type, tcflag_t cflag) 2920 { 2921 struct com_regs regs; 2922 2923 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2924 2925 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2926 } 2927 2928 /* ARGSUSED */ 2929 int 2930 com_kgdb_getc(void *arg) 2931 { 2932 2933 return (com_common_getc(NODEV, &comkgdbregs)); 2934 } 2935 2936 /* ARGSUSED */ 2937 void 2938 com_kgdb_putc(void *arg, int c) 2939 { 2940 2941 com_common_putc(NODEV, &comkgdbregs, c, 0); 2942 } 2943 #endif /* KGDB */ 2944 2945 /* 2946 * helper function to identify the com ports used by 2947 * console or KGDB (and not yet autoconf attached) 2948 */ 2949 int 2950 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2951 { 2952 bus_space_handle_t help; 2953 2954 if (!comconsattached && 2955 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2956 iobase == comcons_info.regs.cr_iobase) 2957 help = comcons_info.regs.cr_ioh; 2958 #ifdef KGDB 2959 else if (!com_kgdb_attached && 2960 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2961 iobase == comkgdbregs.cr_iobase) 2962 help = comkgdbregs.cr_ioh; 2963 #endif 2964 else 2965 return (0); 2966 2967 if (ioh) 2968 *ioh = help; 2969 return (1); 2970 } 2971 2972 /* 2973 * this routine exists to serve as a shutdown hook for systems that 2974 * have firmware which doesn't interact properly with a com device in 2975 * FIFO mode. 2976 */ 2977 bool 2978 com_cleanup(device_t self, int how) 2979 { 2980 struct com_softc *sc = device_private(self); 2981 2982 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2983 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2984 2985 return true; 2986 } 2987 2988 bool 2989 com_suspend(device_t self, const pmf_qual_t *qual) 2990 { 2991 struct com_softc *sc = device_private(self); 2992 2993 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2994 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2995 2996 return true; 2997 } 2998 2999 bool 3000 com_resume(device_t self, const pmf_qual_t *qual) 3001 { 3002 struct com_softc *sc = device_private(self); 3003 3004 com_mutex_enter(sc); 3005 com_loadchannelregs(sc); 3006 com_mutex_exit(sc); 3007 3008 return true; 3009 } 3010
Indexes created Sat Oct 25 16:10:12 GMT 2025