| /src/sys/dev/ic/ |
| ns16450reg.h | 40 #define com_dlbh 1 /* divisor latch high (W) */ macro
|
| st16650reg.h | 43 #define com_dlbh 1 /* divisor latch high (W) */ macro
|
| ns16550reg.h | 43 #define com_dlbh 1 /* divisor latch high (W) */ macro
|
| com.c | 254 [COM_REG_DLBH] = com_dlbh,
|
| /src/sys/arch/i386/stand/lib/ |
| comio_direct.c | 191 rate = inb(combase + com_dlbl) | inb(combase + com_dlbh) << 8;
204 outb(combase + com_dlbh, rate >> 8);
|
| /src/sys/arch/cobalt/stand/boot/ |
| ns16550.c | 55 CSR_WRITE(com_port, com_dlbh, speed >> 8);
|
| /src/sys/arch/hpcmips/stand/lcboot/ |
| com.c | 143 REGWRITE_1(VR4181_SIU_ADDR, com_dlbh, rate >> 8);
|
| /src/sys/arch/evbarm/stand/board/ |
| ns16550.c | 90 OUTB(com_dlbh, rate >> 8);
|
| /src/sys/arch/mmeye/stand/boot/ |
| com.c | 146 CSR_WRITE(com_port, com_dlbh, speed >> 8);
|
| /src/sys/arch/mips/ingenic/ |
| ingenic_com.c | 111 com0addr[com_dlbh] = htole32(rate >> 8);
|
| /src/sys/arch/mips/rmi/ |
| rmixl_com.c | 165 com0addr[com_dlbh] = htobe32(rate >> 8);
|
| /src/sys/arch/ofppc/ofppc/ |
| machdep.c | 437 dlm = bus_space_read_1(&genppc_isa_io_space_tag, comh, com_dlbh);
|
| /src/sys/arch/hp300/dev/ |
| dnkbd.c | 335 bus_space_write_1(bst, bsh, com_dlbh, (divisor >> 8) & 0xff);
|
| /src/sys/arch/mips/sibyte/dev/ |
| sbscn.c | 1776 bus_space_write_1(iot, ioh, com_dlbh, rate >> 8);
|
