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    Searched refs:constrainGenericRegister (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 111 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) &&
112 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI);
131 return RBI.constrainGenericRegister(DstReg, *RC, *MRI);
136 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI))
174 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI))
188 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI);
228 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI);
394 if (!RBI.constrainGenericRegister(DstReg, RC, *MRI))
443 if (!RBI.constrainGenericRegister(Dst0Reg, AMDGPU::SReg_32RegClass, *MRI) ||
444 !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, *MRI) |
    [all...]
AMDGPURegisterBankInfo.cpp 859 constrainGenericRegister(OpReg, AMDGPU::VGPR_32RegClass, MRI);
1105 constrainGenericRegister(Reg, AMDGPU::VGPR_32RegClass, MRI);
1827 return constrainGenericRegister(DstReg, AMDGPU::VGPR_32RegClass, MRI) &&
1828 constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, MRI);
1847 return constrainGenericRegister(SrcReg, AMDGPU::SReg_64RegClass, MRI) &&
1848 constrainGenericRegister(DstReg, AMDGPU::VReg_64RegClass, MRI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstructionSelector.cpp 299 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
696 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
697 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
759 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
760 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
869 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
870 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
984 RBI.constrainGenericRegister(
1064 if (!RBI.constrainGenericRegister(CarryInReg, X86::GR32RegClass, MRI))
1086 !RBI.constrainGenericRegister(CarryOutReg, X86::GR32RegClass, MRI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 820 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI);
956 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1881 RBI.constrainGenericRegister(NewSrc, AArch64::GPR64RegClass, MRI);
2113 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);
2116 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI);
2212 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI);
2425 return RBI.constrainGenericRegister(DefReg, FPRRC, MRI);
2435 if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) {
2513 RBI.constrainGenericRegister(I.getOperand(0).getReg(),
2548 RBI.constrainGenericRegister(I.getOperand(2).getReg()
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
RegisterBankInfo.h 646 constrainGenericRegister(Register Reg, const TargetRegisterClass &RC,
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 223 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
1165 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsInstructionSelector.cpp 112 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
436 return RBI.constrainGenericRegister(DestReg, *DefRC, MRI);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
RegisterBankInfo.cpp 132 const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister(
Utils.cpp 42 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))

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