| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsInstructionSelector.cpp | 152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
266 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI))
281 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI))
305 if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI))
329 if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI))
335 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)
[all...] |
| MipsLegalizerInfo.cpp | 512 return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMInstructionSelector.cpp | 584 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
592 if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI))
603 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
702 if (!constrainSelectedInstRegOperands(*MIBLoad, TII, TRI, RBI))
709 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
716 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
731 if (!constrainSelectedInstRegOperands(*OffsetMIB, TII, TRI, RBI))
742 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
764 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
781 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64InstructionSelector.cpp | 1059 constrainSelectedInstRegOperands(*FCSel, TII, TRI, RBI);
1208 constrainSelectedInstRegOperands(*SelectInst, TII, TRI, RBI);
1392 constrainSelectedInstRegOperands(*TestBitMI, TII, TRI, RBI);
1454 constrainSelectedInstRegOperands(*BranchMI, TII, TRI, RBI);
1611 constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
1616 return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);
1703 constrainSelectedInstRegOperands(*Shl, TII, TRI, RBI);
1760 constrainSelectedInstRegOperands(*Neg, TII, TRI, RBI);
1762 constrainSelectedInstRegOperands(*SShl, TII, TRI, RBI);
1786 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)
[all...] |
| AArch64LegalizerInfo.cpp | 1138 constrainSelectedInstRegOperands(*CAS, *ST->getInstrInfo(),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstructionSelector.cpp | 548 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
585 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
631 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
678 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
831 constrainSelectedInstRegOperands(AndInst, TII, TRI, RBI);
936 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
937 constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI);
1003 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
1004 constrainSelectedInstRegOperands(Set1, TII, TRI, RBI);
1005 constrainSelectedInstRegOperands(Set2, TII, TRI, RBI)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstructionSelector.cpp | 297 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
322 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
330 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
343 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
383 if (!constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI))
420 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
673 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
677 return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
857 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
898 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)
[all...] |
| AMDGPURegisterBankInfo.cpp | 1584 if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this))
1812 if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this))
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| Utils.h | 134 bool constrainSelectedInstRegOperands(MachineInstr &I,
|
| InstructionSelectorImpl.h | 1082 constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI,
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 323 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| Utils.cpp | 134 bool llvm::constrainSelectedInstRegOperands(MachineInstr &I,
|
