| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
| command_table.h | 78 enum controller_id controller_id,
82 enum controller_id controller_id,
92 enum controller_id crtc_id,
|
| command_table_helper2.h | 40 enum controller_id id,
|
| command_table2.h | 78 enum controller_id controller_id,
82 enum controller_id controller_id,
92 enum controller_id crtc_id,
|
| command_table_helper.h | 40 enum controller_id id,
|
| command_table_helper_struct.h | 37 bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);
|
| amdgpu_command_table2.c | 364 uint8_t controller_id; local in function:set_pixel_clock_v7
371 controller_id, &controller_id)) {
391 clk.crtc_id = controller_id;
411 bp_params->target_pixel_clock_100hz, (int)controller_id,
494 bp_params->controller_id, &atom_controller_id))
589 enum controller_id controller_id,
608 enum controller_id controller_id,
[all...] |
| amdgpu_command_table.c | 989 if (CONTROLLER_ID_D1 != bp_params->controller_id)
1022 uint8_t controller_id; local in function:set_pixel_clock_v5
1029 bp_params->controller_id, &controller_id)) {
1030 clk.sPCLKInput.ucCRTC = controller_id;
1079 uint8_t controller_id; local in function:set_pixel_clock_v6
1086 bp_params->controller_id, &controller_id)) {
1106 clk.sPCLKInput.ulCrtcPclkFreq.ucCRTC = controller_id;
1157 uint8_t controller_id; local in function:set_pixel_clock_v7
[all...] |
| amdgpu_command_table_helper.c | 73 enum controller_id id,
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| amdgpu_command_table_helper2.c | 91 enum controller_id id,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| abm.h | 51 bool (*set_pipe)(struct abm *abm, unsigned int controller_id);
60 unsigned int controller_id,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| dce100_hw_sequencer.h | 47 bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
|
| amdgpu_dce100_hw_sequencer.c | 79 uint8_t controller_id,
94 if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){
97 dcb, controller_id + 1, cntl);
103 HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_hw_sequencer.c | 82 #define CNTL_ID(controller_id)\
83 controller_id
88 static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
95 addr = mmDCP0_DVMM_PTE_CONTROL + controller_id *
101 value, 0, DCP, controller_id,
106 value, 1, DCP, controller_id,
111 value, 1, DCP, controller_id,
157 uint8_t controller_id,
177 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
180 dcb, controller_id + 1, cntl)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_hw_sequencer.c | 120 uint8_t controller_id,
138 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
141 dcb, controller_id + 1, cntl);
147 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/include/ |
| bios_parser_types.h | 132 enum controller_id controller_id; member in struct:bp_crtc_source_select
163 enum controller_id controller_id; member in struct:bp_hw_crtc_timing_parameters
211 enum controller_id controller_id; /* (Which CRTC uses this PLL) */ member in struct:bp_pixel_clock_parameters
|
| grph_object_id.h | 76 enum controller_id { enum
250 static inline enum controller_id dal_graphics_object_id_get_controller_id(
254 return (enum controller_id) id.id;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_bios_types.h | 105 enum controller_id id,
128 enum controller_id controller_id,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| clock_source.h | 94 enum controller_id controller_id; member in struct:pixel_clk_params
|
| hw_sequencer_private.h | 90 uint8_t controller_id,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_abm.c | 63 static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id)
80 MASTER_COMM_CMD_REG_BYTE1, controller_id);
209 uint32_t controller_id)
221 dce_abm_set_pipe(&abm_dce->base, controller_id);
231 if (controller_id == 0)
427 unsigned int controller_id,
440 controller_id);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| dce110_timing_generator.h | 103 enum controller_id controller_id; member in struct:dce110_timing_generator
|
| amdgpu_dce110_compressor.c | 215 /* Keep track of enum controller_id FBC is attached to */
259 /* Reset enum controller_id to undefined */
466 unsigned int controller_id_to_index(enum controller_id controller_id)
470 switch (controller_id) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| dm_pp_interface.h | 53 uint32_t controller_id; member in struct:single_display_configuration
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_surface.c | 108 uint32_t controller_id)
110 plane_state->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_timing_generator.c | 235 tg110->controller_id = CONTROLLER_ID_D0 + instance;
|
