| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_mqd_manager_cik.c | 198 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE |
202 m->cp_hqd_pq_control |= PQ_ATC_EN;
210 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
220 m->cp_hqd_pq_control |= NO_UPDATE_RPTR;
324 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE |
333 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
|
| kfd_mqd_manager_v10.c | 176 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
177 m->cp_hqd_pq_control |=
179 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
217 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
294 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
|
| kfd_mqd_manager_v9.c | 214 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
215 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
216 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
255 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
337 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
|
| kfd_mqd_manager_vi.c | 182 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
185 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
186 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
229 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
313 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| cik_structs.h | 98 uint32_t cp_hqd_pq_control; member in struct:cik_mqd
|
| vi_structs.h | 307 uint32_t cp_hqd_pq_control; member in struct:vi_mqd
|
| v9_structs.h | 307 uint32_t cp_hqd_pq_control; member in struct:v9_mqd
|
| v10_structs.h | 824 uint32_t cp_hqd_pq_control; member in struct:v10_compute_mqd
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_amdkfd_gfx_v10.c | 308 2 << REG_GET_FIELD(m->cp_hqd_pq_control,
309 CP_HQD_PQ_CONTROL, QUEUE_SIZE);
|
| amdgpu_amdkfd_gfx_v9.c | 298 2 << REG_GET_FIELD(m->cp_hqd_pq_control,
299 CP_HQD_PQ_CONTROL, QUEUE_SIZE);
|
| amdgpu_gfx_v7_0.c | 2862 u32 cp_hqd_pq_control; member in struct:hqd_registers
2975 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2976 mqd->cp_hqd_pq_control &=
2980 mqd->cp_hqd_pq_control |=
2982 mqd->cp_hqd_pq_control |=
2985 mqd->cp_hqd_pq_control |=
2988 mqd->cp_hqd_pq_control &=
2992 mqd->cp_hqd_pq_control |=
|
| amdgpu_gfx_v10_0.c | 3290 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3292 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3295 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3297 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3298 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3299 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3300 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3301 mqd->cp_hqd_pq_control = tmp;
3415 mqd->cp_hqd_pq_control);
|
| amdgpu_gfx_v9_0.c | 3398 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3400 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3403 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3405 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3406 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3407 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3408 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3409 mqd->cp_hqd_pq_control = tmp;
3522 mqd->cp_hqd_pq_control);
|
| amdgpu_gfx_v8_0.c | 4485 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4487 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4490 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4492 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4494 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4495 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4496 mqd->cp_hqd_pq_control = tmp;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_cik.c | 4478 u32 cp_hqd_pq_control; member in struct:hqd_registers
4685 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
4686 mqd->queue_state.cp_hqd_pq_control &=
4689 mqd->queue_state.cp_hqd_pq_control |=
4691 mqd->queue_state.cp_hqd_pq_control |=
4694 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
4696 mqd->queue_state.cp_hqd_pq_control &=
4698 mqd->queue_state.cp_hqd_pq_control |=
4700 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control)
[all...] |
