| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| cik_structs.h | 115 uint32_t cp_mqd_control; member in struct:cik_mqd
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| vi_structs.h | 324 uint32_t cp_mqd_control; member in struct:vi_mqd
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| v9_structs.h | 324 uint32_t cp_mqd_control; member in struct:v9_mqd
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| v10_structs.h | 841 uint32_t cp_mqd_control; member in struct:v10_compute_mqd
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_mqd_manager_cik.c | 119 m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN;
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| kfd_mqd_manager_v10.c | 114 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
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| kfd_mqd_manager_v9.c | 149 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
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| kfd_mqd_manager_vi.c | 117 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT |
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gfx_v7_0.c | 2879 u32 cp_mqd_control; member in struct:hqd_registers
2966 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2967 mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
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| amdgpu_gfx_v10_0.c | 3280 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3281 mqd->cp_mqd_control = tmp;
3405 mqd->cp_mqd_control);
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| amdgpu_gfx_v9_0.c | 3388 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3389 mqd->cp_mqd_control = tmp;
3512 mqd->cp_mqd_control);
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| amdgpu_gfx_v8_0.c | 4475 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4476 mqd->cp_mqd_control = tmp;
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_cik.c | 4495 u32 cp_mqd_control; member in struct:hqd_registers
4673 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);
4674 mqd->queue_state.cp_mqd_control &= ~MQD_VMID_MASK;
4675 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
|
