1 /* $NetBSD: cpu.c,v 1.10 2025/10/12 04:08:26 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2023 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_multiprocessor.h" 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.10 2025/10/12 04:08:26 thorpej Exp $"); 36 37 #include <sys/param.h> 38 39 #include <sys/cpu.h> 40 #include <sys/device.h> 41 #include <sys/kmem.h> 42 #include <sys/reboot.h> 43 #include <sys/sysctl.h> 44 45 #include <riscv/cpu.h> 46 #include <riscv/cpuvar.h> 47 #include <riscv/machdep.h> 48 #include <riscv/sbi.h> 49 #include <riscv/sysreg.h> 50 51 #ifdef MULTIPROCESSOR 52 #define NCPUINFO MAXCPUS 53 #else 54 #define NCPUINFO 1 55 #endif /* MULTIPROCESSOR */ 56 57 static void 58 cache_nullop(vaddr_t va, paddr_t pa, psize_t sz) 59 { 60 } 61 62 void (*cpu_sdcache_wbinv_range)(vaddr_t, paddr_t, psize_t) = cache_nullop; 63 void (*cpu_sdcache_inv_range)(vaddr_t, paddr_t, psize_t) = cache_nullop; 64 void (*cpu_sdcache_wb_range)(vaddr_t, paddr_t, psize_t) = cache_nullop; 65 66 u_int riscv_dcache_align = CACHE_LINE_SIZE; 67 u_int riscv_dcache_align_mask = CACHE_LINE_SIZE - 1; 68 69 struct cpu_arch { 70 uint64_t ca_id; 71 const char *ca_name; 72 }; 73 74 struct cpu_arch cpu_arch_sifive[] = { 75 { 76 .ca_id = CPU_SIFIVE_ARCH_7SERIES, 77 .ca_name = "7-Series Processor (E7, S7, U7 series)", 78 }, 79 { }, // terminator 80 }; 81 82 struct cpu_arch cpu_arch_thead[] = { 83 { 84 .ca_id = 0, 85 .ca_name = "9-Series Processor (C9, E9 series)", 86 }, 87 { }, // terminator 88 }; 89 90 struct cpu_vendor { 91 uint32_t cv_id; 92 const char *cv_name; 93 struct cpu_arch *cv_arch; 94 } cpu_vendors[] = { 95 { 96 .cv_id = CPU_VENDOR_SIFIVE, 97 .cv_name = "SiFive", 98 .cv_arch = cpu_arch_sifive, 99 }, 100 { 101 .cv_id = CPU_VENDOR_THEAD, 102 .cv_name = "T-Head", 103 .cv_arch = cpu_arch_thead, 104 }, 105 }; 106 107 /* 108 * Our exported cpu_info structs; indexed by BP as 0 and APs [1, ncpu - 1] 109 */ 110 struct cpu_info cpu_info_store[NCPUINFO] = { 111 [0] = { 112 .ci_cpl = IPL_HIGH, 113 .ci_curlwp = &lwp0, 114 .ci_tlb_info = &pmap_tlb0_info, 115 #ifdef MULTIPROCESSOR 116 .ci_flags = CPUF_PRIMARY | CPUF_PRESENT | CPUF_RUNNING, 117 #endif 118 } 119 }; 120 121 /* 122 * setup the per-cpu sysctl tree. 123 */ 124 static void 125 cpu_setup_sysctl(device_t dv, struct cpu_info *ci) 126 { 127 const struct sysctlnode *cpunode = NULL; 128 129 sysctl_createv(NULL, 0, NULL, &cpunode, 130 CTLFLAG_PERMANENT, 131 CTLTYPE_NODE, device_xname(dv), NULL, 132 NULL, 0, NULL, 0, 133 CTL_MACHDEP, 134 CTL_CREATE, CTL_EOL); 135 136 if (cpunode == NULL) 137 return; 138 } 139 140 141 static void 142 cpu_identify(device_t self, struct cpu_info *ci) 143 { 144 const register_t mvendorid = sbi_get_mvendorid().value; 145 const register_t marchid = sbi_get_marchid().value; 146 const uint32_t mimpid = sbi_get_mimpid().value; 147 struct cpu_arch *cv_arch = NULL; 148 const char *cv_name = NULL; 149 const char *ca_name = NULL; 150 char vendor[128]; 151 char arch[128]; 152 153 for (size_t i = 0; i < __arraycount(cpu_vendors); i++) { 154 if (mvendorid == cpu_vendors[i].cv_id) { 155 cv_name = cpu_vendors[i].cv_name; 156 cv_arch = cpu_vendors[i].cv_arch; 157 break; 158 } 159 } 160 161 if (cv_arch != NULL) { 162 for (size_t i = 0; cv_arch[i].ca_name != NULL; i++) { 163 if (marchid == cv_arch[i].ca_id) { 164 ca_name = cv_arch[i].ca_name; 165 break; 166 } 167 } 168 } 169 170 if (cv_name == NULL) { 171 snprintf(vendor, sizeof(vendor), "vendor %" PRIxREGISTER, mvendorid); 172 cv_name = vendor; 173 } 174 if (ca_name == NULL) { 175 snprintf(arch, sizeof(arch), "arch %" PRIxREGISTER, marchid); 176 ca_name = arch; 177 } 178 179 aprint_naive("\n"); 180 aprint_normal(": %s %s imp. %" PRIx32 "\n", cv_name, ca_name, mimpid); 181 aprint_verbose_dev(ci->ci_dev, 182 "vendor 0x%" PRIxREGISTER " arch. %" PRIxREGISTER " imp. %" PRIx32 "\n", 183 mvendorid, marchid, mimpid); 184 } 185 186 187 void 188 cpu_attach(device_t dv, cpuid_t hartid) 189 { 190 struct cpu_info *ci; 191 192 /* Check for the BP */ 193 if (hartid == cpu_bphartid) { 194 ci = curcpu(); 195 KASSERTMSG(ci == &cpu_info_store[0], "ci %p", ci); 196 ci->ci_cpuid = hartid; 197 ci->ci_cpu_freq = riscv_timer_frequency_get(); 198 } else { 199 #ifdef MULTIPROCESSOR 200 if ((boothowto & RB_MD1) != 0) { 201 aprint_naive("\n"); 202 aprint_normal(": multiprocessor boot disabled\n"); 203 return; 204 } 205 206 KASSERT(hartid < MAXCPUS); 207 KASSERT(cpu_hartindex[hartid] < MAXCPUS); 208 209 ci = &cpu_info_store[cpu_hartindex[hartid]]; 210 211 ci->ci_cpl = IPL_HIGH; 212 ci->ci_cpuid = hartid; 213 214 if (!cpu_hatched_p(cpu_hartindex[hartid])) { 215 ci->ci_dev = dv; 216 device_set_private(dv, ci); 217 ci->ci_index = -1; 218 219 aprint_naive(": disabled\n"); 220 aprint_normal(": disabled (unresponsive)\n"); 221 return; 222 } 223 #else /* MULTIPROCESSOR */ 224 aprint_naive(": disabled\n"); 225 aprint_normal(": disabled (uniprocessor kernel)\n"); 226 return; 227 #endif /* MULTIPROCESSOR */ 228 } 229 230 ci->ci_dev = dv; 231 device_set_private(dv, ci); 232 233 const char * const xname = device_xname(dv); 234 235 evcnt_attach_dynamic(&ci->ci_ev_fpu_loads, EVCNT_TYPE_MISC, NULL, 236 xname, "fpu loads"); 237 evcnt_attach_dynamic(&ci->ci_ev_fpu_saves, EVCNT_TYPE_MISC, NULL, 238 xname, "fpu saves"); 239 evcnt_attach_dynamic(&ci->ci_ev_fpu_reenables, EVCNT_TYPE_MISC, NULL, 240 xname, "fpu reenables"); 241 242 cpu_identify(dv, ci); 243 244 #ifdef MULTIPROCESSOR 245 kcpuset_create(&ci->ci_shootdowncpus, true); 246 247 ipi_init(ci); 248 249 kcpuset_create(&ci->ci_multicastcpus, true); 250 kcpuset_create(&ci->ci_watchcpus, true); 251 kcpuset_create(&ci->ci_ddbcpus, true); 252 253 if (hartid != cpu_bphartid) { 254 mi_cpu_attach(ci); 255 } 256 #endif /* MULTIPROCESSOR */ 257 cpu_setup_sysctl(dv, ci); 258 } 259 260 #ifdef MULTIPROCESSOR 261 /* 262 * Initialise a secondary processor. 263 * 264 * printf isn't available as kmutex(9) relies on curcpu which isn't setup yet. 265 * 266 */ 267 void __noasan 268 cpu_init_secondary_processor(u_int cpuindex) 269 { 270 cpu_set_hatched(cpuindex); 271 272 /* 273 * return to assembly to wait for cpu_boot_secondary_processors 274 */ 275 } 276 277 278 /* 279 * When we are called, the MMU and caches are on and we are running on the stack 280 * of the idlelwp for this cpu. 281 */ 282 void 283 cpu_hatch(struct cpu_info *ci, unsigned long cpuindex) 284 { 285 KASSERT(curcpu() == ci); 286 287 // Show this CPU as present. 288 atomic_or_ulong(&ci->ci_flags, CPUF_PRESENT); 289 290 ci->ci_cpu_freq = riscv_timer_frequency_get(); 291 292 riscv_timer_init(); 293 294 kcpuset_set(cpus_hatched, cpu_index(ci)); 295 kcpuset_set(cpus_running, cpu_index(ci)); 296 297 /* 298 * clear my bit of the mailbox to tell cpu_boot_secondary_processors(). 299 * Consider that if there are cpu0, 1, 2, 3, and cpu2 is unresponsive, 300 * ci_index for each would be cpu0=0, cpu1=1, cpu2=undef, cpu3=2. 301 * therefore we have to use device_unit instead of ci_index for mbox. 302 */ 303 304 cpu_clr_mbox(cpuindex); 305 } 306 #endif /* MULTIPROCESSOR */ 307
Indexes created Sun Oct 12 09:09:55 GMT 2025