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Searched refs:cpu_ip3_enable (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/mips/cavium/
octeon_intr.c	281 cpu->cpu_ip3_enable[0] \|= __BIT(CIU_INT_MBOX_31_16); 291 cpu->cpu_ip3_enable[bank], 298 mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]); 383 cpu->cpu_ip3_enable[bank] \|= irq_mask; 384 mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]); 390 cpu->cpu_ip3_enable[bank] \|= irq_mask; 391 mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]); 448 cpu->cpu_ip3_enable[bank] &= ~irq_mask; 449 mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]); 497 & cpu->cpu_ip3_enable[0] [all...]
octeonvar.h	`98 uint64_t cpu_ip3_enable[NBANKS]; member in struct:cpu_softc`

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