| /src/sys/external/bsd/drm2/include/linux/ |
| cpufreq.h | 44 } cpuinfo; member in struct:cpufreq_policy
51 policy->cpuinfo.max_freq = cpufreq_get(curcpu());
|
| /src/sys/arch/sparc/sparc/ |
| cache.h | 122 #define GUESS_CACHE_ALIAS_BITS ((cpuinfo.cacheinfo.c_totalsize - 1) & ~PGOFSET)
123 #define GUESS_CACHE_ALIAS_DIST (cpuinfo.cacheinfo.c_totalsize)
219 #define cache_flush_page(va,ctx) cpuinfo.vcache_flush_page(va,ctx)
220 #define cache_flush_segment(vr,vs,ctx) cpuinfo.vcache_flush_segment(vr,vs,ctx)
221 #define cache_flush_region(vr,ctx) cpuinfo.vcache_flush_region(vr,ctx)
222 #define cache_flush_context(ctx) cpuinfo.vcache_flush_context(ctx)
223 #define cache_flush(va,len) cpuinfo.cache_flush(va,len)
225 #define pcache_flush_page(pa,flag) cpuinfo.pcache_flush_page(pa,flag)
227 #define CACHEINFO cpuinfo.cacheinfo
|
| intr.c | 221 cpuinfo.ci_intrcnt[15].ev_count++;
222 cpuinfo.ci_data.cpu_nintr++;
225 if ((*cpuinfo.get_asyncflt)(&afsr, &afva) == 0) {
228 cpuinfo.mid, bits,
240 if (cpuinfo.master == 0) {
312 cpuinfo.ci_sintrcnt[15].ev_count++;
313 cpuinfo.ci_data.cpu_nintr++;
315 if (cpuinfo.mailbox) {
317 uint8_t msg = *(uint8_t *)cpuinfo.mailbox;
342 switch (cpuinfo.msg_lev15.tag)
[all...] |
| eeprom.c | 85 (cpuinfo.cpu_type != CPUTYP_4_100 &&
86 cpuinfo.cpu_type != CPUTYP_4_200))
|
| trap.c | 279 XCALL0(*cpuinfo.pure_vcache_flush, CPUSET_ALL);
281 (*cpuinfo.pure_vcache_flush)();
316 if (cpuinfo.fplwp != l)
318 l, cpuinfo.fplwp);
321 cpuinfo.fplwp = NULL;
368 XCALL0(*cpuinfo.pure_vcache_flush, CPUSET_ALL);
370 (*cpuinfo.pure_vcache_flush)();
415 if (!cpuinfo.fpupresent) {
447 if (cpuinfo.fplwp != l) {
451 if (cpuinfo.fplwp != NULL)
[all...] |
| cache.c | 128 if (cpuinfo.flags & SUN4_IOCACHE) {
197 if (cpuinfo.mxcc && CACHEINFO.ec_totalsize > 0) {
700 /*if (cpuinfo.cpu_type == CPUTYP_HS_MBUS) -- more work than it's worth */
746 if (cpuinfo.cpu_type == CPUTYP_HS_MBUS) {
796 FXCALL3(cpuinfo.sp_vcache_flush_range,
797 cpuinfo.ft_vcache_flush_range,
800 cpuinfo.sp_vcache_flush_range((int)base, len, ctx);
809 FXCALL3(cpuinfo.sp_vcache_flush_segment,
810 cpuinfo.ft_vcache_flush_segment,
822 FXCALL2(cpuinfo.sp_vcache_flush_region
[all...] |
| timer_sun4m.c | 78 #define counterreg4m cpuinfo.counterreg_4m
130 if (cpi == cpuinfo.ci_self) {
215 if ((++cpuinfo.ci_schedstate.spc_schedticks & 7) == 0 && schedhz != 0) {
225 raise_ipi(&cpuinfo, IPL_SCHED); /* sched_cookie->pil */
|
| kgdb_machdep.c | 216 while (cpuinfo.flags & CPUFLG_PAUSED)
217 cache_flush((void *)__UNVOLATILE(&cpuinfo.flags),
218 sizeof(cpuinfo.flags));
|
| mkclock.c | 114 if (cpuinfo.cpu_type != CPUTYP_4_300 &&
115 cpuinfo.cpu_type != CPUTYP_4_400)
261 if (cpuinfo.cpu_type == CPUTYP_4_300 ||
262 cpuinfo.cpu_type == CPUTYP_4_400) {
|
| cpu.c | 545 if (cpuinfo.hotfix)
546 (*cpuinfo.hotfix)(&cpuinfo);
549 fpu_init(&cpuinfo);
552 cpuinfo.cache_enable();
554 cpuinfo.flags |= CPUFLG_HATCHED;
646 if (cpuinfo.mid == cpi->mid ||
702 cpuinfo.cache_flush_all();
738 mybit = (1 << cpuinfo.ci_cpuid);
779 cpuinfo.ci_xpmsg_mutex_fail.ev_count++
[all...] |
| oclock.c | 98 (cpuinfo.cpu_type != CPUTYP_4_100 &&
99 cpuinfo.cpu_type != CPUTYP_4_200))
|
| timer_sun4.c | 137 if ((++cpuinfo.ci_schedstate.spc_schedticks & 7) == 0) {
|
| core_machdep.c | 96 if (l == cpuinfo.fplwp)
|
| vm_machdep.c | 151 cpuinfo.cache_flush(bp->b_data, len);
230 if (l1 == cpuinfo.fplwp)
306 if (l == cpuinfo.fplwp)
|
| syscall.c | 184 if (cpuinfo.fplwp != l)
186 l, cpuinfo.fplwp);
189 cpuinfo.fplwp = NULL;
|
| memreg.c | 259 (*cpuinfo.get_asyncflt)(&afsr, &afva);
342 if ((*cpuinfo.get_asyncflt)(&afsr, &afva) != 0)
|
| timer.c | 309 if (cpuinfo.cpu_type != CPUTYP_4_300 &&
310 cpuinfo.cpu_type != CPUTYP_4_400)
|
| autoconf.c | 188 cpuinfo.classlvl);
310 cpuinfo.master = 1;
311 getcpuinfo(&cpuinfo, 0);
332 pmap_bootstrap(cpuinfo.mmu_ncontext,
333 cpuinfo.mmu_nregion,
334 cpuinfo.mmu_nsegment);
442 cpuinfo.intreg_4m = (struct icr_pi *)
726 switch (cpuinfo.cpu_type) {
742 cpuinfo.cpu_type);
973 if (cpuinfo.cpu_type == CPUTYP_4_100
[all...] |
| pmap.c | 1348 if (cpuinfo.mxcc) {
1420 cpuinfo.ctx_tbl[0] = SRMMU_TEINVALID;
2295 (*cpuinfo.pure_vcache_flush)();
3110 if (cpuinfo.cpu_type != CPUTYP_4_400) {
3257 cpuinfo.vpage[0] = (void *)p, p += NBPG;
3258 cpuinfo.vpage[1] = (void *)p, p += NBPG;
3483 * enable cache on message buffer and cpuinfo.
3486 /* Enable cache on message buffer and cpuinfo */
3549 ncontext = cpuinfo.mmu_ncontext;
3642 cpuinfo.ctx_tbl = (int *)roundup((u_int)p, ctxtblsize)
[all...] |
| /src/sys/arch/sparc/include/ |
| userret.h | 67 cpuinfo.ci_want_ast = 0;
69 } while (cpuinfo.ci_want_ast);
91 if ((tf->tf_psr & PSR_EF) != 0 && cpuinfo.fplwp != l)
|
| cpu.h | 171 * The cpuinfo structure. This structure maintains information about one
230 #define HASSUN4_MMU3L (cpuinfo.sun4_mmu3l)
416 #define cpuinfo (*(struct cpu_info *)CPUINFO_VA) macro
417 #define curcpu() (cpuinfo.ci_self)
418 #define curlwp (cpuinfo.ci_curlwp)
421 #define cpu_number() (cpuinfo.ci_cpuid)
451 ((framep)->fp > (u_int)cpuinfo.eintstack - INT_STACK_SIZE && \
452 (framep)->fp < (u_int)cpuinfo.eintstack)
477 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, cpuinfo.ci_want_ast = 1)
|
| pmap.h | 376 #define pmap_zero_page (*cpuinfo.zero_page)
377 #define pmap_copy_page (*cpuinfo.copy_page)
|
| /src/sys/compat/linux/arch/alpha/ |
| linux_osf1.c | 687 struct osf1_cpu_info cpuinfo; local in function:linux_sys_osf1_getsysinfo
717 memset(&cpuinfo, 0, sizeof(cpuinfo));
723 cpuinfo.current_cpu = unit;
724 cpuinfo.cpus_in_box = ncpus;
725 cpuinfo.cpu_type = LOCATE_PCS(hwrpb, unit)->pcs_proc_type;
726 cpuinfo.ncpus = ncpus;
727 cpuinfo.cpus_present = ncpus;
728 cpuinfo.cpus_running = ncpus;
729 cpuinfo.cpu_binding = 1
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_llc.c | 39 max_khz = policy->cpuinfo.max_freq;
|
| /src/sys/arch/sparc/dev/ |
| obio.c | 271 if (cpuinfo.cpu_type == CPUTYP_4_100 && (addr & 0xf0000000))
273 if (cpuinfo.cpu_type != CPUTYP_4_100 && !(addr & 0xf0000000))
|
