| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 139 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
375 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
406 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
407 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
408 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_display_rq_dlg_helpers.c | 194 dml_print("DML_RQ_DLG_CALC: crq_expansion_mode = 0x%0x\n", rq_regs.crq_expansion_mode);
|
| display_mode_structs.h | 511 unsigned int crq_expansion_mode; member in struct:_vcs_dpi_display_rq_regs_st
|
| amdgpu_dml1_display_rq_dlg_calc.c | 261 rq_regs->crq_expansion_mode = 1;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hubp.c | 209 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
1064 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
1274 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
1306 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
1307 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
1308 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 218 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
|
| amdgpu_dcn10_hubp.c | 557 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
872 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
|
| amdgpu_dcn10_hw_sequencer.c | 206 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 224 rq_regs->crq_expansion_mode = 1;
|
| amdgpu_display_rq_dlg_calc_20v2.c | 224 rq_regs->crq_expansion_mode = 1;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 204 rq_regs->crq_expansion_mode = 1;
|
