| /src/sys/arch/arm/dts/ |
| rk3399-crypto.dtsi | 33 clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>,
34 <&cru SCLK_CRYPTO1>, <&cru ACLK_DMAC1_PERILP>;
36 assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
38 resets = <&cru SRST_CRYPTO1>;
|
| rk3328-crypto.dtsi | 13 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
14 <&cru SCLK_CRYPTO>;
16 resets = <&cru SRST_CRYPTO>;
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| rk3066a.dtsi | 9 #include <dt-bindings/clock/rk3066a-cru.h>
37 clocks = <&cru ARMCLK>;
69 clocks = <&cru ACLK_LCDC0>,
70 <&cru DCLK_LCDC0>,
71 <&cru HCLK_LCDC0>;
74 resets = <&cru SRST_LCDC0_AXI>,
75 <&cru SRST_LCDC0_AHB>,
76 <&cru SRST_LCDC0_DCLK>;
95 clocks = <&cru ACLK_LCDC1>,
96 <&cru DCLK_LCDC1>
203 cru: clock-controller@20000000 { label
[all...] |
| rk3xxx.dtsi | 42 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
44 assigned-clocks = <&cru ACLK_GPU>;
46 resets = <&cru SRST_GPU>;
56 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
57 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
78 clocks = <&cru CORE_PERI>;
85 clocks = <&cru CORE_PERI>
[all...] |
| rk3288.dtsi | 7 #include <dt-bindings/clock/rk3288-cru.h>
61 resets = <&cru SRST_CORE0>;
65 clocks = <&cru ARMCLK>;
72 resets = <&cru SRST_CORE1>;
76 clocks = <&cru ARMCLK>;
83 resets = <&cru SRST_CORE2>;
87 clocks = <&cru ARMCLK>;
94 resets = <&cru SRST_CORE3>;
98 clocks = <&cru ARMCLK>;
199 clocks = <&cru PCLK_TIMER>, <&xin24m>
862 cru: clock-controller@ff760000 { label
[all...] |
| rk322x.dtsi | 7 #include <dt-bindings/clock/rk3228-cru.h>
32 resets = <&cru SRST_CORE0>;
36 clocks = <&cru ARMCLK>;
44 resets = <&cru SRST_CORE1>;
54 resets = <&cru SRST_CORE2>;
64 resets = <&cru SRST_CORE3>;
140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
153 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>
484 cru: clock-controller@110e0000 { label
[all...] |
| rv1108.dtsi | 6 #include <dt-bindings/clock/rv1108-cru.h>
36 clocks = <&cru ARMCLK>;
101 clocks = <&cru ACLK_DMAC>;
121 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
136 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
151 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
165 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>
456 cru: clock-controller@20200000 { label
[all...] |
| rk3188.dtsi | 9 #include <dt-bindings/clock/rk3188-cru.h>
27 clocks = <&cru ARMCLK>;
29 resets = <&cru SRST_CORE0>;
37 resets = <&cru SRST_CORE1>;
45 resets = <&cru SRST_CORE2>;
53 resets = <&cru SRST_CORE3>;
119 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
122 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>
195 cru: clock-controller@20000000 { label
[all...] |
| rk3036.dtsi | 7 #include <dt-bindings/clock/rk3036-cru.h>
41 resets = <&cru SRST_CORE0>;
47 clocks = <&cru ARMCLK>;
54 resets = <&cru SRST_CORE1>;
111 assigned-clocks = <&cru SCLK_GPU>;
113 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
116 resets = <&cru SRST_GPU>;
125 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>
330 cru: clock-controller@20000000 { label
[all...] |
| rk3228-evb.dts | 40 assigned-clocks = <&cru SCLK_MAC_SRC>;
56 clocks = <&cru SCLK_MAC_PHY>;
57 resets = <&cru SRST_MACPHY>;
66 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
| rk3188-bqedison2qc.dts | 225 &cru {
226 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
227 <&cru ACLK_CPU>,
228 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
229 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
230 <&cru PCLK_PERI>;
450 clocks = <&cru SCLK_I2S0>
[all...] |
| rk3229-evb.dts | 149 assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
150 assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
195 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/ |
| rk3399.dtsi | 6 #include <dt-bindings/clock/rk3399-cru.h>
75 clocks = <&cru ARMCLKL>;
87 clocks = <&cru ARMCLKL>;
99 clocks = <&cru ARMCLKL>;
111 clocks = <&cru ARMCLKL>;
123 clocks = <&cru ARMCLKB>;
135 clocks = <&cru ARMCLKB>;
211 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
212 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>
1369 cru: clock-controller@ff760000 { label
[all...] |
| rk3568.dtsi | 6 #include <dt-bindings/clock/rk3568-cru.h>
226 cru: clock-controller@fdd20000 { label
227 compatible = "rockchip,rk3568-cru";
264 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
265 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
269 resets = <&cru SRST_SDMMC2>;
278 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>
[all...] |
| px30.dtsi | 6 #include <dt-bindings/clock/px30-cru.h>
47 clocks = <&cru ARMCLK>;
59 clocks = <&cru ARMCLK>;
71 clocks = <&cru ARMCLK>;
83 clocks = <&cru ARMCLK>;
249 clocks = <&cru HCLK_HOST>,
250 <&cru HCLK_OTG>,
251 <&cru SCLK_OTG_ADP>;
257 clocks = <&cru HCLK_SDMMC>,
258 <&cru SCLK_SDMMC>
781 cru: clock-controller@ff2b0000 { label
[all...] |
| rk3328.dtsi | 6 #include <dt-bindings/clock/rk3328-cru.h>
42 clocks = <&cru ARMCLK>;
55 clocks = <&cru ARMCLK>;
68 clocks = <&cru ARMCLK>;
81 clocks = <&cru ARMCLK>;
215 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
227 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
239 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>
763 cru: clock-controller@ff440000 { label
[all...] |
| rk3308.dtsi | 7 #include <dt-bindings/clock/rk3308-cru.h>
46 clocks = <&cru ARMCLK>;
189 assigned-clocks = <&cru USB480M>;
191 clocks = <&cru SCLK_USBPHY_REF>;
233 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
246 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
259 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>
734 cru: clock-controller@ff500000 { label
[all...] |
| rk3368.dtsi | 6 #include <dt-bindings/clock/rk3368-cru.h>
182 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
183 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
187 resets = <&cru SRST_MMC0>;
196 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
197 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>
637 cru: clock-controller@ff760000 { label
[all...] |
| rk3399-gru-scarlet.dtsi | 307 clocks = <&cru SCLK_TESTCLKOUT1>;
330 clocks = <&cru SCLK_TESTCLKOUT1>;
365 &cru {
367 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
368 <&cru PLL_NPLL>,
369 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
370 <&cru PCLK_PERIHP>,
371 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>
[all...] |
| rk3399-rockpro64-v2.dts | 20 clocks = <&cru SCLK_I2S_8CH_OUT>;
|
| rk3399-rockpro64.dts | 20 clocks = <&cru SCLK_I2S_8CH_OUT>;
|
| rk3326-odroid-go2.dts | 230 &cru {
231 assigned-clocks = <&cru PLL_NPLL>,
232 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
233 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
234 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
235 <&cru PLL_CPLL>;
300 clocks = <&cru SCLK_I2S1_OUT>
[all...] |
| rk3399-gru.dtsi | 351 &cru {
353 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
354 <&cru PLL_NPLL>,
355 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
356 <&cru PCLK_PERIHP>,
357 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
358 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>
[all...] |
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
| rk3066a-cru.h | 1 /* $NetBSD: rk3066a-cru.h,v 1.1.1.2 2020/01/03 14:33:04 skrll Exp $ */
12 #include <dt-bindings/clock/rk3188-cru-common.h>
|
| rk3188-cru.h | 1 /* $NetBSD: rk3188-cru.h,v 1.1.1.2 2020/01/03 14:33:06 skrll Exp $ */
12 #include <dt-bindings/clock/rk3188-cru-common.h>
|
