| /src/sys/net/ |
| slcompress.h | 123 struct cstate { struct
124 struct cstate *cs_next; /* next most recently used cstate (xmit only) */
143 struct cstate *last_cs; /* most recently used tstate */
157 struct cstate tstate[MAX_STATES]; /* xmit connection states */
158 struct cstate rstate[MAX_STATES]; /* receive connection states */
|
| slcompress.c | 74 struct cstate *tstate = comp->tstate;
98 struct cstate *tstate = comp->tstate;
177 struct cstate *cs = comp->last_cs->cs_next;
220 struct cstate *lcs;
221 struct cstate *lastcs = comp->last_cs;
234 * Didn't find it -- re-use oldest cstate. Send an
478 struct cstate *cs;
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_base.c | 84 nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate,
93 u32 freq = cstate->domain[domain->name];
110 voltage = nvkm_volt_map(volt, cstate->voltage, temp);
118 struct nvkm_cstate *cstate)
124 if (!pstate || !cstate)
128 return cstate;
141 list_for_each_entry_from_reverse(cstate, &pstate->list, head) {
142 if (nvkm_cstate_valid(clk, cstate, max_volt, clk->temp))
146 return cstate;
152 struct nvkm_cstate *cstate; local in function:nvkm_cstate_get
171 struct nvkm_cstate *cstate; local in function:nvkm_cstate_prog
233 struct nvkm_cstate *cstate = NULL; local in function:nvkm_cstate_new
381 struct nvkm_cstate *cstate; local in function:nvkm_pstate_info
423 struct nvkm_cstate *cstate, *temp; local in function:nvkm_pstate_del
439 struct nvkm_cstate *cstate; local in function:nvkm_pstate_new
[all...] |
| nouveau_nvkm_subdev_clk_gf100.c | 279 calc_clk(struct gf100_clk *clk, struct nvkm_cstate *cstate, int idx, int dom)
282 u32 freq = cstate->domain[dom];
299 clk1 = cstate->domain[nv_clk_src_hubk06];
330 gf100_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
335 if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
336 (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) ||
337 (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) ||
338 (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) ||
339 (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) ||
340 (ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) |
[all...] |
| nouveau_nvkm_subdev_clk_gk104.c | 293 struct nvkm_cstate *cstate, int idx, int dom)
296 u32 freq = cstate->domain[dom];
313 clk1 = cstate->domain[nv_clk_src_hubk06];
344 gk104_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
349 if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
350 (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) ||
351 (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) ||
352 (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) ||
353 (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) ||
354 (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_pmu)) |
[all...] |
| nouveau_nvkm_subdev_clk_gt215.c | 279 calc_clk(struct gt215_clk *clk, struct nvkm_cstate *cstate,
282 int ret = gt215_pll_info(&clk->base, idx, pll, cstate->domain[dom],
290 calc_host(struct gt215_clk *clk, struct nvkm_cstate *cstate)
293 u32 kHz = cstate->domain[nv_clk_src_host];
464 gt215_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
470 if ((ret = calc_clk(clk, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
471 (ret = calc_clk(clk, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||
472 (ret = calc_clk(clk, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||
473 (ret = calc_clk(clk, cstate, 0x21, 0x0000, nv_clk_src_vdec)) ||
474 (ret = calc_host(clk, cstate)))
[all...] |
| nouveau_nvkm_subdev_clk_nv40.c | 151 nv40_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
154 int gclk = cstate->domain[nv_clk_src_core];
155 int sclk = cstate->domain[nv_clk_src_shader];
|
| nouveau_nvkm_subdev_clk_mcp77.c | 208 mcp77_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
211 const int shader = cstate->domain[nv_clk_src_shader];
212 const int core = cstate->domain[nv_clk_src_core];
213 const int vdec = cstate->domain[nv_clk_src_vdec];
|
| nouveau_nvkm_subdev_clk_nv50.c | 373 nv50_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
379 const int shader = cstate->domain[nv_clk_src_shader];
380 const int core = cstate->domain[nv_clk_src_core];
381 const int vdec = cstate->domain[nv_clk_src_vdec];
382 const int dom6 = cstate->domain[nv_clk_src_dom6];
|
| nouveau_nvkm_subdev_clk_gk20a.c | 485 gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
489 return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] *
|
| nouveau_nvkm_subdev_clk_gm20b.c | 469 gm20b_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
476 ret = gk20a_pllg_calc_mnp(&clk->base, cstate->domain[nv_clk_src_gpc] *
481 clk->new_uv = volt->vid[cstate->voltage].uv;
|
| /src/sys/arch/x86/x86/ |
| powernow.c | 417 DPRINTF(("%s: cstate->state_table.freq=%d\n",
448 struct powernow_cpu_state *cstate; local in function:powernow_k7_states
455 cstate = sc->sc_state;
473 cstate->sgtc = psb->ttime * cstate->fsb;
475 if (cstate->sgtc < 100 * cstate->fsb)
476 cstate->sgtc = 100 * cstate->fsb;
502 if (abs(cstate->fsb - pst->pll) > 5
614 struct powernow_cpu_state *cstate = sc->sc_state; local in function:powernow_k7_decode_pst
722 struct powernow_cpu_state *cstate; local in function:powernow_k8_states
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/ttm/ |
| ttm_page_alloc.c | 227 enum ttm_caching_state cstate)
231 if (cstate == tt_cached)
234 if (cstate == tt_wc)
448 enum ttm_caching_state cstate, unsigned cpages)
452 switch (cstate) {
475 int ttm_flags, enum ttm_caching_state cstate,
493 int ttm_flags, enum ttm_caching_state cstate,
522 cstate, cpages);
525 ttm_flags, cstate,
547 cstate, cpages)
[all...] |
| ttm_page_alloc_dma.c | 332 static enum pool_type ttm_to_type(int flags, enum ttm_caching_state cstate)
338 if (cstate == tt_cached)
340 else if (cstate == tt_uncached)
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/ |
| nouveau_nvkm_engine_device_ctrl.c | 81 struct nvkm_cstate *cstate; local in function:nvkm_control_mthd_pstate_attr
118 list_for_each_entry(cstate, &pstate->list, head) {
119 lo = min(lo, cstate->domain[domain->name]);
120 hi = max(hi, cstate->domain[domain->name]);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/ |
| therm.h | 70 int cstate; member in struct:nvkm_therm
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/therm/ |
| nouveau_nvkm_subdev_therm_base.c | 142 if (therm->cstate) {
143 duty = therm->cstate;
174 if (!dir || (dir < 0 && fan < therm->cstate) ||
175 (dir > 0 && fan > therm->cstate)) {
177 therm->cstate = fan;
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_ddi.c | 3309 tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
3311 struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
3314 if (!cstate->dc3co_exitline)
3317 val = I915_READ(EXITLINE(cstate->cpu_transcoder));
3319 I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
3323 tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
3326 struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
3328 if (!cstate->dc3co_exitline)
3331 exit_scanlines = cstate->dc3co_exitline;
3333 val = I915_READ(EXITLINE(cstate->cpu_transcoder))
[all...] |
| intel_psr.c | 547 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
549 if (!cstate || !cstate->hw.active)
553 drm_mode_vrefresh(&cstate->hw.adjusted_mode));
|
| /src/sys/arch/x86/include/ |
| specialreg.h | 385 #define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x0000000f)
|
