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    Searched refs:ctr_el0 (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/compiler_rt/dist/lib/builtins/
clear_cache.c 138 uint64_t ctr_el0;
139 __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
145 const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
151 const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
  /src/sys/stand/efiboot/bootaa64/
cache.S 49 mrs x3, ctr_el0
54 mrs x3, ctr_el0
  /src/sys/arch/aarch64/aarch64/
cpufunc_asm_armv8.S 48 mrs x3, ctr_el0
trap.c 314 ci->ci_cpuname, "ctr_el0 trap");
316 /* trap CTR_EL0 access from EL0 on this cpu */
391 /* mrs x?,ctr_el0 */
394 uint64_t ctr_el0 = reg_ctr_el0_read(); local in function:emul_aarch64_insn
395 ctr_el0 &= ~CTR_EL0_USR_MASK;
396 ctr_el0 |= (ctr_el0_usr & CTR_EL0_USR_MASK);
397 tf->tf_reg[Xt] = ctr_el0;
db_machdep.c 601 SHOW_ARMREG(ctr_el0);
  /src/sys/arch/aarch64/include/
armreg.h 113 AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register

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