| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/ |
| nouveau_dispnv50_pior507d.c | 30 pior507d_ctrl(struct nv50_core *core, int or, u32 ctrl,
36 ctrl |= asyh->or.depth << 16;
37 ctrl |= asyh->or.nvsync << 13;
38 ctrl |= asyh->or.nhsync << 12;
41 evo_data(push, ctrl);
48 .ctrl = pior507d_ctrl,
|
| nouveau_dispnv50_sor507d.c | 30 sor507d_ctrl(struct nv50_core *core, int or, u32 ctrl,
36 ctrl |= asyh->or.depth << 16;
37 ctrl |= asyh->or.nvsync << 13;
38 ctrl |= asyh->or.nhsync << 12;
41 evo_data(push, ctrl);
48 .ctrl = sor507d_ctrl,
|
| nouveau_dispnv50_dac907d.c | 30 dac907d_ctrl(struct nv50_core *core, int or, u32 ctrl,
36 evo_data(push, ctrl);
43 .ctrl = dac907d_ctrl,
|
| nouveau_dispnv50_sor907d.c | 32 sor907d_ctrl(struct nv50_core *core, int or, u32 ctrl,
38 evo_data(push, ctrl);
45 .ctrl = sor907d_ctrl,
|
| nouveau_dispnv50_sorc37d.c | 30 sorc37d_ctrl(struct nv50_core *core, int or, u32 ctrl,
36 evo_data(push, ctrl);
43 .ctrl = sorc37d_ctrl,
|
| nouveau_dispnv50_dac507d.c | 30 dac507d_ctrl(struct nv50_core *core, int or, u32 ctrl,
40 evo_data(push, ctrl);
48 .ctrl = dac507d_ctrl,
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_dmacgp102.c | 38 int ctrl = chan->chid.ctrl; local in function:gp102_disp_dmac_init
42 nvkm_wr32(device, 0x611494 + (ctrl * 0x0010), chan->push);
43 nvkm_wr32(device, 0x611498 + (ctrl * 0x0010), 0x00010000);
44 nvkm_wr32(device, 0x61149c + (ctrl * 0x0010), 0x00000001);
45 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000010, 0x00000010);
46 nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), 0x00000000);
47 nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013);
51 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x80000000))
55 nvkm_rd32(device, 0x610490 + (ctrl * 0x10)))
[all...] |
| nouveau_nvkm_engine_disp_piocgf119.c | 40 int ctrl = chan->chid.ctrl; local in function:gf119_disp_pioc_fini
43 nvkm_mask(device, 0x610490 + (ctrl * 0x10), 0x00000001, 0x00000000);
45 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x00030000))
49 nvkm_rd32(device, 0x610490 + (ctrl * 0x10)));
59 int ctrl = chan->chid.ctrl; local in function:gf119_disp_pioc_init
63 nvkm_wr32(device, 0x610490 + (ctrl * 0x10), 0x00000001);
65 u32 tmp = nvkm_rd32(device, 0x610490 + (ctrl * 0x10));
70 nvkm_rd32(device, 0x610490 + (ctrl * 0x10)))
[all...] |
| nouveau_nvkm_engine_disp_piocnv50.c | 40 int ctrl = chan->chid.ctrl; local in function:nv50_disp_pioc_fini
43 nvkm_mask(device, 0x610200 + (ctrl * 0x10), 0x00000001, 0x00000000);
45 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000))
49 nvkm_rd32(device, 0x610200 + (ctrl * 0x10)));
59 int ctrl = chan->chid.ctrl; local in function:nv50_disp_pioc_init
62 nvkm_wr32(device, 0x610200 + (ctrl * 0x10), 0x00002000);
64 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000))
68 nvkm_rd32(device, 0x610200 + (ctrl * 0x10)))
[all...] |
| nouveau_nvkm_engine_disp_dmacgf119.c | 48 int ctrl = chan->chid.ctrl; local in function:gf119_disp_dmac_fini
52 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00001010, 0x00001000);
53 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000003, 0x00000000);
55 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x001e0000))
59 nvkm_rd32(device, 0x610490 + (ctrl * 0x10)));
68 int ctrl = chan->chid.ctrl; local in function:gf119_disp_dmac_init
72 nvkm_wr32(device, 0x610494 + (ctrl * 0x0010), chan->push);
73 nvkm_wr32(device, 0x610498 + (ctrl * 0x0010), 0x00010000)
[all...] |
| nouveau_nvkm_engine_disp_dmacnv50.c | 89 int ctrl = chan->chid.ctrl; local in function:nv50_disp_dmac_fini
93 nvkm_mask(device, 0x610200 + (ctrl * 0x0010), 0x00001010, 0x00001000);
94 nvkm_mask(device, 0x610200 + (ctrl * 0x0010), 0x00000003, 0x00000000);
96 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x001e0000))
100 nvkm_rd32(device, 0x610200 + (ctrl * 0x10)));
109 int ctrl = chan->chid.ctrl; local in function:nv50_disp_dmac_init
113 nvkm_wr32(device, 0x610204 + (ctrl * 0x0010), chan->push);
114 nvkm_wr32(device, 0x610208 + (ctrl * 0x0010), 0x00010000)
[all...] |
| nouveau_nvkm_engine_disp_hdmigm200.c | 36 const u32 ctrl = scdc & 0x3; local in function:gm200_hdmi_scdc
38 nvkm_mask(device, 0x61c5bc + hoff, 0x00000003, ctrl);
|
| nouveau_nvkm_engine_disp_sorg84.c | 35 .ctrl = g84_hdmi_ctrl,
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dsi_dcs_backlight.c | 102 u8 ctrl = 0; local in function:dcs_disable_backlight
107 &ctrl, sizeof(ctrl));
109 ctrl &= ~CONTROL_DISPLAY_BL;
110 ctrl &= ~CONTROL_DISPLAY_DD;
111 ctrl &= ~CONTROL_DISPLAY_BCTRL;
114 &ctrl, sizeof(ctrl));
127 u8 ctrl = 0; local in function:dcs_enable_backlight
132 &ctrl, sizeof(ctrl))
[all...] |
| /src/sys/arch/evbarm/tsarm/ |
| tslcd.c | 175 uint8_t ctrl; local in function:tslcd_writereg
181 ctrl = GPIO_GET(PHDR);
185 ctrl |= 0x10; /* assert RS */
186 ctrl &= ~0x20; /* assert WR */
188 ctrl &= ~0x30; /* de-assert WR, de-assert RS */
190 GPIO_SET(PHDR, ctrl);
196 ctrl |= 0x8;
197 GPIO_SET(PHDR, ctrl);
203 ctrl &= ~0x8;
204 GPIO_SET(PHDR, ctrl);
221 uint8_t ret, ctrl; local in function:tslcd_readreg
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/ |
| nouveau_nvkm_engine_device_ctrl.c | 29 #include "ctrl.h"
40 nvkm_control_mthd_pstate_info(struct nvkm_control *ctrl, void *data, u32 size)
45 struct nvkm_clk *clk = ctrl->device->clk;
48 nvif_ioctl(&ctrl->object, "control pstate info size %d\n", size);
50 nvif_ioctl(&ctrl->object, "control pstate info vers %d\n",
73 nvkm_control_mthd_pstate_attr(struct nvkm_control *ctrl, void *data, u32 size)
78 struct nvkm_clk *clk = ctrl->device->clk;
86 nvif_ioctl(&ctrl->object, "control pstate attr size %d\n", size);
88 nvif_ioctl(&ctrl->object,
146 nvkm_control_mthd_pstate_user(struct nvkm_control *ctrl, void *data, u32 size
177 struct nvkm_control *ctrl = nvkm_control(object); local in function:nvkm_control_mthd
200 struct nvkm_control *ctrl; local in function:nvkm_control_new
[all...] |
| /src/sys/arch/arm/arm32/ |
| arm11_pmc.c | 117 uint32_t ctrl; local in function:delay
131 ctrl = arm11_pmc_ctrl_read();
132 if (ctrl & ARM11_PMCCTL_CCR) {
137 ctrl &= ~(ARM11_PMCCTL_CR0|ARM11_PMCCTL_CR1);
138 arm11_pmc_ctrl_write(ctrl);
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_pwm.c | 112 uint32_t ctrl, octrl; local in function:sunxi_pwm_enable
114 octrl = ctrl = PWM_READ(sc, PWM_CH_CTRL);
116 ctrl |= (PWM_CH0_EN | SCLK_CH0_GATING);
118 ctrl &= ~(PWM_CH0_EN | SCLK_CH0_GATING);
120 if (ctrl != octrl)
121 PWM_WRITE(sc, PWM_CH_CTRL, ctrl);
130 uint32_t ctrl, ch_period; local in function:sunxi_pwm_get_config
132 ctrl = PWM_READ(sc, PWM_CH_CTRL);
139 conf->polarity = (ctrl & PWM_CH0_ACT_STA) ? PWM_ACTIVE_HIGH : PWM_ACTIVE_LOW;
150 uint32_t ctrl, ch_period local in function:sunxi_pwm_set_config
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/i2c/ |
| nouveau_nvkm_subdev_i2c_auxg94.c | 51 u32 ctrl, timeout; local in function:g94_i2c_aux_init
56 ctrl = nvkm_rd32(device, 0x00e4e4 + (aux->ch * 0x50));
59 AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl);
62 } while (ctrl & 0x03010000);
68 ctrl = nvkm_rd32(device, 0x00e4e4 + (aux->ch * 0x50));
71 AUX_ERR(&aux->base, "magic wait %08x", ctrl);
75 } while ((ctrl & 0x03000000) != urep);
87 u32 ctrl, stat, timeout, retries = 0; local in function:g94_i2c_aux_xfer
112 ctrl = nvkm_rd32(device, 0x00e4e4 + base);
113 ctrl &= ~0x0001f1ff
[all...] |
| nouveau_nvkm_subdev_i2c_auxgm200.c | 51 u32 ctrl, timeout; local in function:gm200_i2c_aux_init
56 ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50));
59 AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl);
62 } while (ctrl & 0x03010000);
68 ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50));
71 AUX_ERR(&aux->base, "magic wait %08x", ctrl);
75 } while ((ctrl & 0x03000000) != urep);
87 u32 ctrl, stat, timeout, retries = 0; local in function:gm200_i2c_aux_xfer
112 ctrl = nvkm_rd32(device, 0x00d954 + base);
113 ctrl &= ~0x0001f1ff
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/therm/ |
| nouveau_nvkm_subdev_therm_nv50.c | 33 pwm_info(struct nvkm_therm *therm, int *line, int *ctrl, int *indx)
38 *ctrl = 0x00e100;
43 *ctrl = 0x00e100;
48 *ctrl = 0x00e28c;
52 nvkm_error(subdev, "unknown pwm ctrl for gpio %d\n", *line);
64 int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id); local in function:nv50_fan_pwm_ctrl
66 nvkm_mask(device, ctrl, 0x00010001 << line, data << line);
74 int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id) local in function:nv50_fan_pwm_get
91 int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id); local in function:nv50_fan_pwm_set
[all...] |
| /src/usr.bin/unifdef/ |
| unifdefall.sh | 13 unifdef -s "$@" | sort | uniq > $tmp/ctrl
17 comm -23 $tmp/ctrl $tmp/alldef > $tmp/undef
18 comm -12 $tmp/ctrl $tmp/alldef > $tmp/def
|
| /src/sys/arch/arm/rockchip/ |
| rk_pwm.c | 117 uint32_t ctrl, octrl; local in function:rk_pwm_enable
119 octrl = ctrl = PWM_READ(sc, PWM0_CTRL);
121 ctrl |= CTRL_PWM_EN;
123 ctrl &= ~CTRL_PWM_EN;
125 if (ctrl != octrl)
126 PWM_WRITE(sc, PWM0_CTRL, ctrl);
139 uint32_t ctrl, period, duty;
142 ctrl = PWM_READ(sc, PWM0_CTRL);
146 if (ctrl & CTRL_CLK_SEL) {
147 div = __SHIFTOUT(ctrl, CTRL_SCALE) * 2
171 uint32_t ctrl; local in function:rk_pwm_set_config
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/ |
| nouveau_debugfs.h | 14 struct nvif_object ctrl; member in struct:nouveau_debugfs
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| ramnv40.h | 11 u32 ctrl; member in struct:nv40_ram
|
