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    Searched refs:ctrl1 (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.h 184 * lower part of ctrl1 and they get shifted into position when writing
188 u32 ctrl1; member in struct:intel_dpll_hw_state
intel_dpll_mgr.c 1004 val |= pll->state.hw_state.ctrl1 << (id * 6);
1076 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1114 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1372 u32 ctrl1, cfgcr1, cfgcr2; local in function:skl_ddi_hdmi_pll_dividers
1379 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1381 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1400 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1409 u32 ctrl1; local in function:skl_ddi_dp_set_dpll_hw_state
1415 ctrl1 = DPLL_CTRL1_OVERRIDE(0)
    [all...]
intel_ddi.c 1633 * ctrl1 register is already shifted for each pll, just use 0 to get
1636 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1639 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
intel_display.c 13673 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
imx6ull-colibri.dtsi 460 pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
imx7-colibri.dtsi 767 pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
  /src/sys/dev/ic/
bwivar.h 132 uint32_t ctrl1; member in struct:bwi_desc64

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