1 /* $NetBSD: cuda.c,v 1.33 2025/09/22 12:50:13 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.33 2025/09/22 12:50:13 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/proc.h> 37 #include <sys/mutex.h> 38 39 #include <sys/bus.h> 40 #include <machine/autoconf.h> 41 #include <machine/pio.h> 42 #include <dev/clock_subr.h> 43 44 #include <dev/i2c/i2cvar.h> 45 #include <dev/i2c/i2c_calls.h> 46 #include <dev/i2c/i2c_enum.h> 47 48 #include <macppc/dev/viareg.h> 49 #include <macppc/dev/cudavar.h> 50 51 #include <dev/ofw/openfirm.h> 52 #include <dev/adb/adbvar.h> 53 #include "opt_cuda.h" 54 55 #ifdef CUDA_DEBUG 56 #define DPRINTF printf 57 #else 58 #define DPRINTF while (0) printf 59 #endif 60 61 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */ 62 #define CUDA_IDLE 0x2 /* the bus is currently idle */ 63 #define CUDA_OUT 0x3 /* sending out a command */ 64 #define CUDA_IN 0x4 /* receiving data */ 65 #define CUDA_POLLING 0x5 /* polling - II only */ 66 67 static void cuda_attach(device_t, device_t, void *); 68 static int cuda_match(device_t, struct cfdata *, void *); 69 static void cuda_autopoll(void *, int); 70 71 static int cuda_intr(void *); 72 73 typedef struct _cuda_handler { 74 int (*handler)(void *, int, uint8_t *); 75 void *cookie; 76 } CudaHandler; 77 78 struct cuda_softc { 79 device_t sc_dev; 80 void *sc_ih; 81 CudaHandler sc_handlers[16]; 82 struct todr_chip_handle sc_todr; 83 struct adb_bus_accessops sc_adbops; 84 struct i2c_controller sc_i2c; 85 bus_space_tag_t sc_memt; 86 bus_space_handle_t sc_memh; 87 88 /* 89 * We provide our own i2c device enumeration method, so we 90 * need to subclass our device handle. 91 */ 92 struct devhandle_impl sc_devhandle_impl; 93 94 int sc_node; 95 int sc_state; 96 int sc_waiting; 97 int sc_polling; 98 int sc_sent; 99 int sc_out_length; 100 int sc_received; 101 int sc_iic_done; 102 int sc_error; 103 /* time */ 104 uint32_t sc_tod; 105 uint32_t sc_autopoll; 106 kcondvar_t sc_todev; 107 kmutex_t sc_todevmtx; 108 /* ADB */ 109 void (*sc_adb_handler)(void *, int, uint8_t *); 110 void *sc_adb_cookie; 111 uint32_t sc_i2c_read_len; 112 /* internal buffers */ 113 uint8_t sc_in[256]; 114 uint8_t sc_out[256]; 115 }; 116 117 CFATTACH_DECL_NEW(cuda, sizeof(struct cuda_softc), 118 cuda_match, cuda_attach, NULL, NULL); 119 120 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t); 121 static inline uint8_t cuda_read_reg(struct cuda_softc *, int); 122 static void cuda_idle(struct cuda_softc *); 123 static void cuda_tip(struct cuda_softc *); 124 static void cuda_clear_tip(struct cuda_softc *); 125 static void cuda_in(struct cuda_softc *); 126 static void cuda_out(struct cuda_softc *); 127 static void cuda_toggle_ack(struct cuda_softc *); 128 static void cuda_ack_off(struct cuda_softc *); 129 static int cuda_intr_state(struct cuda_softc *); 130 131 static void cuda_init(struct cuda_softc *); 132 133 /* 134 * send a message to Cuda. 135 */ 136 /* cookie, flags, length, data */ 137 static int cuda_send(void *, int, int, uint8_t *); 138 static void cuda_poll(void *); 139 static void cuda_adb_poll(void *); 140 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *); 141 142 static int cuda_error_handler(void *, int, uint8_t *); 143 144 static int cuda_todr_handler(void *, int, uint8_t *); 145 static int cuda_todr_set(todr_chip_handle_t, struct timeval *); 146 static int cuda_todr_get(todr_chip_handle_t, struct timeval *); 147 148 static int cuda_adb_handler(void *, int, uint8_t *); 149 static void cuda_final(device_t); 150 151 static struct cuda_attach_args *cuda0 = NULL; 152 153 /* ADB bus attachment stuff */ 154 static int cuda_adb_send(void *, int, int, int, uint8_t *); 155 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *); 156 157 /* i2c stuff */ 158 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 159 void *, size_t, int); 160 161 static const struct i2c_deventry cuda_i2c_devices[] = { 162 { .name = "videopll", 163 .compat = "aapl,valkyrie-videopll", 164 .addr = 0x50, 165 .data = "/valkyrie" }, 166 167 { .name = "sgsmix", 168 .compat = "st,tda7433", 169 .addr = 0x8a, 170 .data = "/perch" }, 171 172 I2C_DEVENTRY_EOL 173 }; 174 175 static int 176 cuda_i2c_enumerate_devices(device_t dev, devhandle_t call_handle, void *v) 177 { 178 struct i2c_enumerate_devices_args *args = v; 179 const struct i2c_deventry *entry; 180 bool cbrv; 181 182 for (entry = cuda_i2c_devices; entry->name != NULL; entry++) { 183 if (OF_finddevice((const char *)entry->data) == -1) { 184 continue; 185 } 186 cbrv = i2c_enumerate_device(dev, args, entry->name, 187 entry->compat, 0, entry->addr, devhandle_invalid()); 188 if (!cbrv) { 189 break; 190 } 191 } 192 193 return 0; 194 } 195 196 static device_call_t 197 cuda_devhandle_lookup_device_call(devhandle_t handle, const char *name, 198 devhandle_t *call_handlep) 199 { 200 if (strcmp(name, I2C_ENUMERATE_DEVICES_STR) == 0) { 201 return cuda_i2c_enumerate_devices; 202 } 203 204 /* Defer everything else to the "super". */ 205 return NULL; 206 } 207 208 static int 209 cuda_match(device_t parent, struct cfdata *cf, void *aux) 210 { 211 struct confargs *ca = aux; 212 213 if (ca->ca_nreg < 8) 214 return 0; 215 216 if (ca->ca_nintr < 4) 217 return 0; 218 219 if (strcmp(ca->ca_name, "via-cuda") == 0) { 220 return 10; /* beat adb* at obio? */ 221 } 222 223 return 0; 224 } 225 226 static void 227 cuda_attach(device_t parent, device_t self, void *aux) 228 { 229 struct confargs *ca = aux; 230 struct cuda_softc *sc = device_private(self); 231 static struct cuda_attach_args caa; 232 int irq = ca->ca_intr[0]; 233 int node, i, child; 234 char name[32]; 235 236 sc->sc_dev = self; 237 node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1"); 238 if (node) 239 OF_getprop(node, "interrupts", &irq, 4); 240 241 aprint_normal(" irq %d", irq); 242 243 sc->sc_node = ca->ca_node; 244 sc->sc_memt = ca->ca_tag; 245 246 sc->sc_sent = 0; 247 sc->sc_received = 0; 248 sc->sc_waiting = 0; 249 sc->sc_polling = 0; 250 sc->sc_state = CUDA_NOTREADY; 251 sc->sc_error = 0; 252 sc->sc_i2c_read_len = 0; 253 254 cv_init(&sc->sc_todev, "cuda_event"); 255 mutex_init(&sc->sc_todevmtx, MUTEX_DEFAULT, IPL_NONE); 256 257 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr, 258 ca->ca_reg[1], 0, &sc->sc_memh) != 0) { 259 260 aprint_normal(": unable to map registers\n"); 261 return; 262 } 263 sc->sc_ih = intr_establish_xname(irq, IST_EDGE, IPL_TTY, cuda_intr, sc, 264 device_xname(self)); 265 printf("\n"); 266 267 for (i = 0; i < 16; i++) { 268 sc->sc_handlers[i].handler = NULL; 269 sc->sc_handlers[i].cookie = NULL; 270 } 271 272 cuda_init(sc); 273 274 /* now attach children */ 275 config_interrupts(self, cuda_final); 276 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc); 277 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc); 278 279 child = OF_child(ca->ca_node); 280 while (child != 0) { 281 282 if (OF_getprop(child, "name", name, 32) == 0) 283 continue; 284 if (strncmp(name, "adb", 4) == 0) { 285 286 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc); 287 sc->sc_adbops.cookie = sc; 288 sc->sc_adbops.send = cuda_adb_send; 289 sc->sc_adbops.poll = cuda_adb_poll; 290 sc->sc_adbops.autopoll = cuda_autopoll; 291 sc->sc_adbops.set_handler = cuda_adb_set_handler; 292 config_found(self, &sc->sc_adbops, nadb_print, 293 CFARGS(.iattr = "adb_bus")); 294 } else if (strncmp(name, "rtc", 4) == 0) { 295 296 sc->sc_todr.todr_gettime = cuda_todr_get; 297 sc->sc_todr.todr_settime = cuda_todr_set; 298 sc->sc_todr.todr_dev = self; 299 todr_attach(&sc->sc_todr); 300 } 301 child = OF_peer(child); 302 } 303 304 caa.cookie = sc; 305 caa.set_handler = cuda_set_handler; 306 caa.send = cuda_send; 307 caa.poll = cuda_poll; 308 #if notyet 309 config_found(self, &caa, cuda_print, CFARGS_NONE); 310 #endif 311 312 /* 313 * There are no OF nodes for our I2C devices, so we provide 314 * our own enumeration method. 315 */ 316 iic_tag_init(&sc->sc_i2c); 317 sc->sc_i2c.ic_cookie = sc; 318 sc->sc_i2c.ic_exec = cuda_i2c_exec; 319 320 iicbus_attach_with_devhandle(self, &sc->sc_i2c, 321 devhandle_subclass(device_handle(self), 322 &sc->sc_devhandle_impl, 323 cuda_devhandle_lookup_device_call)); 324 325 if (cuda0 == NULL) 326 cuda0 = &caa; 327 } 328 329 static void 330 cuda_init(struct cuda_softc *sc) 331 { 332 uint8_t reg; 333 334 reg = cuda_read_reg(sc, vDirB); 335 reg |= 0x30; /* register B bits 4 and 5: outputs */ 336 cuda_write_reg(sc, vDirB, reg); 337 338 reg = cuda_read_reg(sc, vDirB); 339 reg &= 0xf7; /* register B bit 3: input */ 340 cuda_write_reg(sc, vDirB, reg); 341 342 reg = cuda_read_reg(sc, vACR); 343 reg &= ~vSR_OUT; /* make sure SR is set to IN */ 344 cuda_write_reg(sc, vACR, reg); 345 346 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 347 348 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 349 350 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 351 cuda_idle(sc); /* set ADB bus state to idle */ 352 353 /* sort of a device reset */ 354 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 355 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 356 cuda_idle(sc); /* reset state to idle */ 357 delay(150); 358 cuda_tip(sc); /* signal start of frame */ 359 delay(150); 360 cuda_toggle_ack(sc); 361 delay(150); 362 cuda_clear_tip(sc); 363 delay(150); 364 cuda_idle(sc); /* back to idle state */ 365 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 366 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 367 } 368 369 static void 370 cuda_final(device_t dev) 371 { 372 struct cuda_softc *sc = device_private(dev); 373 374 sc->sc_polling = 0; 375 } 376 377 static inline void 378 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value) 379 { 380 381 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value); 382 } 383 384 static inline uint8_t 385 cuda_read_reg(struct cuda_softc *sc, int offset) 386 { 387 388 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset); 389 } 390 391 static int 392 cuda_set_handler(void *cookie, int type, 393 int (*handler)(void *, int, uint8_t *), void *hcookie) 394 { 395 struct cuda_softc *sc = cookie; 396 CudaHandler *me; 397 398 if ((type >= 0) && (type < 16)) { 399 me = &sc->sc_handlers[type]; 400 me->handler = handler; 401 me->cookie = hcookie; 402 return 0; 403 } 404 return -1; 405 } 406 407 static int 408 cuda_send(void *cookie, int poll, int length, uint8_t *msg) 409 { 410 struct cuda_softc *sc = cookie; 411 int s; 412 413 DPRINTF("cuda_send %08x\n", (uint32_t)cookie); 414 if (sc->sc_state == CUDA_NOTREADY) 415 return -1; 416 417 s = splhigh(); 418 419 if (sc->sc_state == CUDA_IDLE /*&& 420 (cuda_read_reg(sc, vBufB) & vPB3) == vPB3*/) { 421 /* fine */ 422 DPRINTF("chip is idle\n"); 423 } else { 424 DPRINTF("cuda state is %d\n", sc->sc_state); 425 if (sc->sc_waiting == 0) { 426 sc->sc_waiting = 1; 427 } else { 428 splx(s); 429 return -1; 430 } 431 } 432 433 sc->sc_error = 0; 434 memcpy(sc->sc_out, msg, length); 435 sc->sc_out_length = length; 436 sc->sc_sent = 0; 437 438 if (sc->sc_waiting != 1) { 439 440 delay(150); 441 sc->sc_state = CUDA_OUT; 442 cuda_out(sc); 443 cuda_write_reg(sc, vSR, sc->sc_out[0]); 444 cuda_ack_off(sc); 445 cuda_tip(sc); 446 } 447 sc->sc_waiting = 1; 448 449 if (sc->sc_polling || poll || cold) { 450 cuda_poll(sc); 451 } 452 453 splx(s); 454 455 return 0; 456 } 457 458 static void 459 cuda_poll(void *cookie) 460 { 461 struct cuda_softc *sc = cookie; 462 int s; 463 464 DPRINTF("polling\n"); 465 while ((sc->sc_state != CUDA_IDLE) || 466 (cuda_intr_state(sc)) || 467 (sc->sc_waiting == 1)) { 468 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) { 469 s = splhigh(); 470 cuda_intr(sc); 471 splx(s); 472 } 473 } 474 } 475 476 static void 477 cuda_adb_poll(void *cookie) 478 { 479 struct cuda_softc *sc = cookie; 480 int s; 481 482 s = splhigh(); 483 cuda_intr(sc); 484 splx(s); 485 } 486 487 static void 488 cuda_idle(struct cuda_softc *sc) 489 { 490 uint8_t reg; 491 492 reg = cuda_read_reg(sc, vBufB); 493 reg |= (vPB4 | vPB5); 494 cuda_write_reg(sc, vBufB, reg); 495 } 496 497 static void 498 cuda_tip(struct cuda_softc *sc) 499 { 500 uint8_t reg; 501 502 reg = cuda_read_reg(sc, vBufB); 503 reg &= ~vPB5; 504 cuda_write_reg(sc, vBufB, reg); 505 } 506 507 static void 508 cuda_clear_tip(struct cuda_softc *sc) 509 { 510 uint8_t reg; 511 512 reg = cuda_read_reg(sc, vBufB); 513 reg |= vPB5; 514 cuda_write_reg(sc, vBufB, reg); 515 } 516 517 static void 518 cuda_in(struct cuda_softc *sc) 519 { 520 uint8_t reg; 521 522 reg = cuda_read_reg(sc, vACR); 523 reg &= ~vSR_OUT; 524 cuda_write_reg(sc, vACR, reg); 525 } 526 527 static void 528 cuda_out(struct cuda_softc *sc) 529 { 530 uint8_t reg; 531 532 reg = cuda_read_reg(sc, vACR); 533 reg |= vSR_OUT; 534 cuda_write_reg(sc, vACR, reg); 535 } 536 537 static void 538 cuda_toggle_ack(struct cuda_softc *sc) 539 { 540 uint8_t reg; 541 542 reg = cuda_read_reg(sc, vBufB); 543 reg ^= vPB4; 544 cuda_write_reg(sc, vBufB, reg); 545 } 546 547 static void 548 cuda_ack_off(struct cuda_softc *sc) 549 { 550 uint8_t reg; 551 552 reg = cuda_read_reg(sc, vBufB); 553 reg |= vPB4; 554 cuda_write_reg(sc, vBufB, reg); 555 } 556 557 static int 558 cuda_intr_state(struct cuda_softc *sc) 559 { 560 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 561 } 562 563 static int 564 cuda_intr(void *arg) 565 { 566 struct cuda_softc *sc = arg; 567 int ending, type; 568 uint8_t reg; 569 570 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */ 571 DPRINTF("["); 572 if ((reg & 0x80) == 0) { 573 DPRINTF("irq %02x]", reg); 574 return 0; /* No interrupts to process */ 575 } 576 DPRINTF(":"); 577 578 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */ 579 580 switch_start: 581 switch (sc->sc_state) { 582 case CUDA_IDLE: 583 /* 584 * This is an unexpected packet, so grab the first (dummy) 585 * byte, set up the proper vars, and tell the chip we are 586 * starting to receive the packet by setting the TIP bit. 587 */ 588 sc->sc_in[1] = cuda_read_reg(sc, vSR); 589 DPRINTF("start: %02x", sc->sc_in[1]); 590 if (cuda_intr_state(sc) == 0) { 591 /* must have been a fake start */ 592 DPRINTF(" ... fake start\n"); 593 if (sc->sc_waiting) { 594 /* start over */ 595 delay(150); 596 sc->sc_state = CUDA_OUT; 597 sc->sc_sent = 0; 598 cuda_out(sc); 599 cuda_write_reg(sc, vSR, sc->sc_out[1]); 600 cuda_ack_off(sc); 601 cuda_tip(sc); 602 } 603 break; 604 } 605 606 cuda_in(sc); 607 cuda_tip(sc); 608 609 sc->sc_received = 1; 610 sc->sc_state = CUDA_IN; 611 DPRINTF(" CUDA_IN"); 612 break; 613 614 case CUDA_IN: 615 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 616 DPRINTF(" %02x", sc->sc_in[sc->sc_received]); 617 ending = 0; 618 if (sc->sc_received > 255) { 619 /* bitch only once */ 620 if (sc->sc_received == 256) { 621 aprint_error_dev(sc->sc_dev, 622 "input overflow\n"); 623 ending = 1; 624 } 625 } else 626 sc->sc_received++; 627 if (sc->sc_received > 3) { 628 if ((sc->sc_in[3] == CMD_IIC) && 629 (sc->sc_received > (sc->sc_i2c_read_len + 4))) { 630 ending = 1; 631 } 632 } 633 634 /* intr off means this is the last byte (end of frame) */ 635 if (cuda_intr_state(sc) == 0) { 636 ending = 1; 637 DPRINTF(".\n"); 638 } else { 639 cuda_toggle_ack(sc); 640 } 641 642 if (ending == 1) { /* end of message? */ 643 644 sc->sc_in[0] = sc->sc_received - 1; 645 646 /* reset vars and signal the end of this frame */ 647 cuda_idle(sc); 648 649 /* check if we have a handler for this message */ 650 type = sc->sc_in[1]; 651 if ((type >= 0) && (type < 16)) { 652 CudaHandler *me = &sc->sc_handlers[type]; 653 654 if (me->handler != NULL) { 655 me->handler(me->cookie, 656 sc->sc_received - 1, &sc->sc_in[1]); 657 } else { 658 aprint_error_dev(sc->sc_dev, 659 "no handler for type %02x\n", type); 660 panic("barf"); 661 } 662 } 663 664 DPRINTF("CUDA_IDLE"); 665 sc->sc_state = CUDA_IDLE; 666 667 sc->sc_received = 0; 668 669 /* 670 * If there is something waiting to be sent out, 671 * set everything up and send the first byte. 672 */ 673 if (sc->sc_waiting == 1) { 674 675 DPRINTF("pending write\n"); 676 delay(1500); /* required */ 677 sc->sc_sent = 0; 678 sc->sc_state = CUDA_OUT; 679 680 /* 681 * If the interrupt is on, we were too slow 682 * and the chip has already started to send 683 * something to us, so back out of the write 684 * and start a read cycle. 685 */ 686 if (cuda_intr_state(sc)) { 687 cuda_in(sc); 688 cuda_idle(sc); 689 sc->sc_sent = 0; 690 sc->sc_state = CUDA_IDLE; 691 sc->sc_received = 0; 692 delay(150); 693 DPRINTF("too slow - incoming message\n"); 694 goto switch_start; 695 } 696 /* 697 * If we got here, it's ok to start sending 698 * so load the first byte and tell the chip 699 * we want to send. 700 */ 701 DPRINTF("sending "); 702 703 cuda_out(sc); 704 cuda_write_reg(sc, vSR, 705 sc->sc_out[sc->sc_sent]); 706 cuda_ack_off(sc); 707 cuda_tip(sc); 708 } 709 } 710 break; 711 712 case CUDA_OUT: 713 (void)cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 714 715 sc->sc_sent++; 716 if (cuda_intr_state(sc)) { /* ADB intr low during write */ 717 718 DPRINTF("incoming msg during send\n"); 719 cuda_in(sc); /* make sure SR is set to IN */ 720 cuda_idle(sc); 721 sc->sc_sent = 0; /* must start all over */ 722 sc->sc_state = CUDA_IDLE; /* new state */ 723 sc->sc_received = 0; 724 sc->sc_waiting = 1; /* must retry when done with 725 * read */ 726 delay(150); 727 goto switch_start; /* process next state right 728 * now */ 729 break; 730 } 731 if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 732 733 sc->sc_waiting = 0; /* done writing */ 734 sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 735 cuda_in(sc); 736 cuda_idle(sc); 737 DPRINTF("done sending\n"); 738 } else { 739 /* send next byte */ 740 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 741 DPRINTF("%02x", sc->sc_out[sc->sc_sent]); 742 cuda_toggle_ack(sc); /* signal byte ready to 743 * shift */ 744 } 745 break; 746 747 case CUDA_NOTREADY: 748 DPRINTF("adb: not yet initialized\n"); 749 break; 750 751 default: 752 DPRINTF("intr: unknown ADB state\n"); 753 break; 754 } 755 756 DPRINTF("]"); 757 return 1; 758 } 759 760 static int 761 cuda_error_handler(void *cookie, int len, uint8_t *data) 762 { 763 struct cuda_softc *sc = cookie; 764 765 /* 766 * something went wrong 767 * byte 3 seems to be the failed command 768 */ 769 sc->sc_error = 1; 770 DPRINTF("cuda error %02x %02x %02x %02x\n", data[0], data[1], data[2], data[3]); 771 cv_signal(&sc->sc_todev); 772 return 0; 773 } 774 775 776 /* real time clock */ 777 778 static int 779 cuda_todr_handler(void *cookie, int len, uint8_t *data) 780 { 781 struct cuda_softc *sc = cookie; 782 783 #ifdef CUDA_DEBUG 784 int i; 785 printf("msg: %02x", data[0]); 786 for (i = 1; i < len; i++) { 787 printf(" %02x", data[i]); 788 } 789 printf("\n"); 790 #endif 791 792 switch(data[2]) { 793 case CMD_READ_RTC: 794 memcpy(&sc->sc_tod, &data[3], 4); 795 break; 796 case CMD_WRITE_RTC: 797 sc->sc_tod = 0xffffffff; 798 break; 799 case CMD_AUTOPOLL: 800 sc->sc_autopoll = 1; 801 break; 802 case CMD_IIC: 803 sc->sc_iic_done = len; 804 break; 805 } 806 cv_signal(&sc->sc_todev); 807 return 0; 808 } 809 810 #define DIFF19041970 2082844800 811 812 static int 813 cuda_todr_get(todr_chip_handle_t tch, struct timeval *tvp) 814 { 815 struct cuda_softc *sc = device_private(tch->todr_dev); 816 int cnt = 0; 817 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC}; 818 819 sc->sc_tod = 0; 820 while (sc->sc_tod == 0) { 821 cuda_send(sc, 0, 2, cmd); 822 823 while ((sc->sc_tod == 0) && (cnt < 10)) { 824 mutex_enter(&sc->sc_todevmtx); 825 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz); 826 mutex_exit(&sc->sc_todevmtx); 827 828 cnt++; 829 } 830 831 if (sc->sc_tod == 0) { 832 aprint_error_dev(sc->sc_dev, 833 "unable to read a sane RTC value\n"); 834 return EIO; 835 } 836 if ((sc->sc_tod > 0xf0000000UL) || 837 (sc->sc_tod < DIFF19041970)) { 838 /* huh? try again */ 839 sc->sc_tod = 0; 840 aprint_verbose_dev(sc->sc_dev, 841 "got garbage reading RTC, trying again\n"); 842 } 843 } 844 845 tvp->tv_sec = sc->sc_tod - DIFF19041970; 846 DPRINTF("tod: %" PRIo64 "\n", tvp->tv_sec); 847 tvp->tv_usec = 0; 848 return 0; 849 } 850 851 static int 852 cuda_todr_set(todr_chip_handle_t tch, struct timeval *tvp) 853 { 854 struct cuda_softc *sc = device_private(tch->todr_dev); 855 uint32_t sec; 856 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 857 858 sec = tvp->tv_sec + DIFF19041970; 859 memcpy(&cmd[2], &sec, 4); 860 sc->sc_tod = 0; 861 if (cuda_send(sc, 0, 6, cmd) == 0) { 862 while (sc->sc_tod == 0) { 863 mutex_enter(&sc->sc_todevmtx); 864 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz); 865 mutex_exit(&sc->sc_todevmtx); 866 } 867 return 0; 868 } 869 aprint_error_dev(sc->sc_dev, "%s failed\n", __func__); 870 return -1; 871 872 } 873 874 /* poweroff and reboot */ 875 876 void 877 cuda_poweroff(void) 878 { 879 struct cuda_softc *sc; 880 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF}; 881 882 if (cuda0 == NULL) 883 return; 884 sc = cuda0->cookie; 885 sc->sc_polling = 1; 886 cuda0->poll(sc); 887 if (cuda0->send(sc, 1, 2, cmd) == 0) 888 while (1); 889 } 890 891 void 892 cuda_restart(void) 893 { 894 struct cuda_softc *sc; 895 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET}; 896 897 if (cuda0 == NULL) 898 return; 899 sc = cuda0->cookie; 900 sc->sc_polling = 1; 901 cuda0->poll(sc); 902 if (cuda0->send(sc, 1, 2, cmd) == 0) 903 while (1); 904 } 905 906 /* ADB message handling */ 907 908 static void 909 cuda_autopoll(void *cookie, int flag) 910 { 911 struct cuda_softc *sc = cookie; 912 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)}; 913 914 if (cmd[2] == sc->sc_autopoll) 915 return; 916 917 sc->sc_autopoll = -1; 918 cuda_send(sc, 0, 3, cmd); 919 while(sc->sc_autopoll == -1) { 920 if (sc->sc_polling || cold) { 921 cuda_poll(sc); 922 } else { 923 mutex_enter(&sc->sc_todevmtx); 924 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz); 925 mutex_exit(&sc->sc_todevmtx); 926 } 927 } 928 } 929 930 static int 931 cuda_adb_handler(void *cookie, int len, uint8_t *data) 932 { 933 struct cuda_softc *sc = cookie; 934 935 if (sc->sc_adb_handler != NULL) { 936 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1, 937 &data[1]); 938 return 0; 939 } 940 return -1; 941 } 942 943 static int 944 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data) 945 { 946 struct cuda_softc *sc = cookie; 947 int i, s = 0; 948 uint8_t packet[16]; 949 950 /* construct an ADB command packet and send it */ 951 packet[0] = CUDA_ADB; 952 packet[1] = command; 953 for (i = 0; i < len; i++) 954 packet[i + 2] = data[i]; 955 if (poll || cold) { 956 s = splhigh(); 957 cuda_poll(sc); 958 } 959 cuda_send(sc, poll, len + 2, packet); 960 if (poll || cold) { 961 cuda_poll(sc); 962 splx(s); 963 } 964 return 0; 965 } 966 967 static int 968 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *), 969 void *hcookie) 970 { 971 struct cuda_softc *sc = cookie; 972 973 /* register a callback for incoming ADB messages */ 974 sc->sc_adb_handler = handler; 975 sc->sc_adb_cookie = hcookie; 976 return 0; 977 } 978 979 /* i2c message handling */ 980 981 static int 982 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send, 983 size_t send_len, void *_recv, size_t recv_len, int flags) 984 { 985 struct cuda_softc *sc = cookie; 986 const uint8_t *send = _send; 987 uint8_t *recv = _recv; 988 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC}; 989 990 DPRINTF("cuda_i2c_exec(%02x)\n", addr); 991 command[2] = addr; 992 993 /* Copy command and output data bytes, if any, to buffer */ 994 if (send_len > 0) 995 memcpy(&command[3], send, uimin((int)send_len, 12)); 996 else if (I2C_OP_READ_P(op) && (recv_len == 0)) { 997 /* 998 * If no data bytes in either direction, it's a "quick" 999 * i2c operation. We don't know how to do a quick_read 1000 * since that requires us to set the low bit of the 1001 * address byte after it has been left-shifted. 1002 */ 1003 sc->sc_error = 0; 1004 return -1; 1005 } 1006 1007 sc->sc_iic_done = 0; 1008 cuda_send(sc, sc->sc_polling, send_len + 3, command); 1009 1010 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 1011 if (sc->sc_polling || cold) { 1012 cuda_poll(sc); 1013 } else { 1014 mutex_enter(&sc->sc_todevmtx); 1015 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz); 1016 mutex_exit(&sc->sc_todevmtx); 1017 } 1018 } 1019 1020 if (sc->sc_error) { 1021 sc->sc_error = 0; 1022 aprint_error_dev(sc->sc_dev, "error doing I2C\n"); 1023 return -1; 1024 } 1025 1026 /* see if we're supposed to do a read */ 1027 if (recv_len > 0) { 1028 sc->sc_iic_done = 0; 1029 command[2] |= 1; 1030 command[3] = 0; 1031 1032 /* 1033 * XXX we need to do something to limit the size of the answer 1034 * - apparently the chip keeps sending until we tell it to stop 1035 */ 1036 sc->sc_i2c_read_len = recv_len; 1037 DPRINTF("rcv_len: %d\n", recv_len); 1038 cuda_send(sc, sc->sc_polling, 3, command); 1039 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 1040 if (sc->sc_polling || cold) { 1041 cuda_poll(sc); 1042 } else { 1043 mutex_enter(&sc->sc_todevmtx); 1044 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz); 1045 mutex_exit(&sc->sc_todevmtx); 1046 } 1047 } 1048 1049 if (sc->sc_error) { 1050 aprint_error_dev(sc->sc_dev, 1051 "error trying to read from I2C\n"); 1052 sc->sc_error = 0; 1053 return -1; 1054 } 1055 } 1056 1057 DPRINTF("received: %d\n", sc->sc_iic_done); 1058 if ((sc->sc_iic_done > 3) && (recv_len > 0)) { 1059 int rlen; 1060 1061 /* we got an answer */ 1062 rlen = uimin(sc->sc_iic_done - 3, recv_len); 1063 memcpy(recv, &sc->sc_in[4], rlen); 1064 #ifdef CUDA_DEBUG 1065 { 1066 int i; 1067 printf("ret:"); 1068 for (i = 0; i < rlen; i++) 1069 printf(" %02x", recv[i]); 1070 printf("\n"); 1071 } 1072 #endif 1073 return rlen; 1074 } 1075 return 0; 1076 } 1077
Indexes created Tue Sep 23 07:09:52 GMT 2025