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    Searched refs:current_state (Results 1 - 25 of 48) sorted by relevancy

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  /src/usr.bin/talk/
msgs.c 52 const char *current_state; variable in typeref:typename:const char *
58 message(current_state);
66 message(current_state);
look_up.c 70 current_state = "Waiting to connect with caller";
106 current_state = "Checking for invitation on caller's machine";
talk.h 46 extern const char *current_state;
invite.c 107 current_state = "Waiting for your party to respond";
153 current_state = "Trying to connect to your party's talk daemon";
init_disp.c 93 current_state = "No connection yet";
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc.c 112 * these structs in dc->current_state representing the currently programmed state.
292 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
320 &dc->current_state->res_ctx.pipe_ctx[i];
353 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
402 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
426 if (dc->current_state->res_ctx.pipe_ctx[i].stream
428 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
448 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
450 pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
485 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream)
    [all...]
amdgpu_dc_stream.c 229 * The given stream is expected to exist in dc->current_state. Otherwise, NULL
236 return dc_stream_get_status_from_state(dc->current_state, stream);
295 res_ctx = &dc->current_state->res_ctx;
342 res_ctx = &dc->current_state->res_ctx;
420 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
431 dc->hwss.update_writeback(dc, wb_info, dc->current_state);
434 dc->hwss.enable_writeback(dc, wb_info, dc->current_state);
487 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
513 &dc->current_state->res_ctx;
541 res_ctx = &dc->current_state->res_ctx
    [all...]
amdgpu_dc_surface.c 156 if (dc->current_state == NULL)
162 &dc->current_state->res_ctx.pipe_ctx[i];
174 &dc->current_state->res_ctx.pipe_ctx[i];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/
amdgpu_clk_mgr.c 76 dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
93 dc->hwss.optimize_pwr_state(dc, dc->current_state);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/
hdcp.h 412 static inline uint8_t current_state(struct mod_hdcp *hdcp) function in typeref:typename:uint8_t
430 return (current_state(hdcp) > HDCP1_STATE_START &&
431 current_state(hdcp) <= HDCP1_STATE_END);
436 return (current_state(hdcp) > HDCP1_DP_STATE_START &&
437 current_state(hdcp) <= HDCP1_DP_STATE_END);
442 return (current_state(hdcp) > HDCP2_STATE_START &&
443 current_state(hdcp) <= HDCP2_STATE_END);
448 return (current_state(hdcp) > HDCP2_DP_STATE_START &&
449 current_state(hdcp) <= HDCP2_DP_STATE_END);
464 return current_state(hdcp) == HDCP_CP_NOT_DESIRED
    [all...]
amdgpu_hdcp1_transition.c 42 switch (current_state(hdcp)) {
166 switch (current_state(hdcp)) {
amdgpu_hdcp.c 263 if (current_state(hdcp) != HDCP_UNINITIALIZED) {
356 if (current_state(hdcp) != HDCP_INITIALIZED)
amdgpu_hdcp1_execution.c 471 switch (current_state(hdcp)) {
505 switch (current_state(hdcp)) {
  /src/sys/arch/xen/xenbus/
xenbus_client.c 108 u_long current_state; local in function:xenbus_switch_state
111 &current_state, 10);
115 if ((XenbusState)current_state == state)
  /src/sys/arch/ia64/unwind/
stackframe.c 631 struct staterecord current_state; variable in typeref:struct:staterecord
830 poprecord(&current_state, rchain->udesc.B2.ecount);
835 poprecord(&current_state, rchain->udesc.B3.ecount);
1004 initrecord(&current_state);
1022 pushrecord(&current_state);
1039 pushrecord(&current_state);
1055 pushrecord(&current_state);
1069 modifyrecord(&current_state, &rchain[i], rdepth);
1076 modifyrecord(&current_state, &rchain[i],
1090 dump_staterecord(&current_state);
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer_debug.c 437 pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
480 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
481 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
482 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
483 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
484 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
485 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
amdgpu_dcn10_hw_sequencer.c 453 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
454 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
455 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
456 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
457 dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
458 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
459 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
762 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
896 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
917 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rs780_dpm.c 386 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); local in function:rs780_force_voltage
388 if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
389 (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
413 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); local in function:rs780_force_fbdiv
415 if (current_state->sclk_low == current_state->sclk_high)
574 struct igp_ps *current_state = rs780_get_ps(old_ps); local in function:rs780_set_uvd_clock_before_set_eng_clock
580 if (new_state->sclk_high >= current_state->sclk_high)
591 struct igp_ps *current_state = rs780_get_ps(old_ps); local in function:rs780_set_uvd_clock_after_set_eng_clock
597 if (new_state->sclk_high < current_state->sclk_high
    [all...]
  /src/sys/dev/raidframe/
rf_states.c 102 RF_AccessState_t current_state = desc->states[current_state_index]; local in function:rf_ContinueRaidAccess
110 current_state = desc->states[current_state_index];
112 switch (current_state) {
154 unit, StateName(current_state),
159 } while (!suspended && current_state != rf_LastState);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 1397 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1398 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1567 if (context->res_ctx.pipe_ctx[i].stream == dc->current_state->res_ctx.pipe_ctx[i].stream)
1569 dc->current_state->res_ctx.pipe_ctx[i].stream_res.gsl_group;
1573 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1583 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], true);
1599 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1600 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1632 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], false);
1637 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i])
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_hw_sequencer.c 967 /*current_state not updated yet*/
968 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1276 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1514 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1516 &dc->current_state->res_ctx.pipe_ctx[i]);
1880 &dc->current_state->res_ctx.pipe_ctx[i];
1912 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
1926 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2044 &dc->current_state->res_ctx.pipe_ctx[i];
2069 &dc->current_state->res_ctx.pipe_ctx[i]
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
amdgpu_dce110_clk_mgr.c 249 if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
amdgpu_rv1_clk_mgr.c 107 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dmub_psr.c 108 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/
amdgpu_irq_service_dce110.c 220 dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;

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