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    Searched refs:cw0 (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/crypto/aes/arch/x86/
aes_via.c 163 uint8_t out[static 16], size_t nblocks, uint32_t cw0)
166 [0] = (cw0
184 uint8_t out[static 16], size_t nblocks, uint32_t cw0)
187 [0] = (cw0
214 const uint32_t cw0 = aesvia_keylen_cw0(nrounds); local
221 aesvia_encN(enc, in, out, 1, cw0);
235 aesvia_encN(enc, inbuf, outbuf, 1, cw0);
255 const uint32_t cw0 = aesvia_keylen_cw0(nrounds); local
262 aesvia_decN(dec, in, out, 1, cw0);
276 aesvia_decN(dec, inbuf, outbuf, 1, cw0);
370 const uint32_t cw0 = aesvia_keylen_cw0(nrounds); local
412 const uint32_t cw0 = aesvia_keylen_cw0(nrounds); local
509 const uint32_t cw0 = aesvia_keylen_cw0(nrounds); local
603 const uint32_t cw0 = aesvia_keylen_cw0(nrounds); local
696 const uint32_t cw0 = aesvia_keylen_cw0(nrounds); local
737 const uint32_t cw0 = aesvia_keylen_cw0(nrounds); local
803 const uint32_t cw0 = aesvia_keylen_cw0(nrounds); local
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
amdgpu_dmub_dcn20.c 101 const struct dmub_window *cw0,
113 dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
117 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
119 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
amdgpu_dmub_srv.c 341 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; local
352 cw0.offset.quad_part = inst_fb->gpu_addr;
353 cw0.region.base = DMUB_CW0_BASE;
354 cw0.region.top = cw0.region.base + inst_fb->size - 1;
368 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
dmub_dcn20.h 167 const struct dmub_window *cw0,
  /src/sys/arch/x86/x86/
via_padlock.c 136 int sesn, i, cw0; local
188 cw0 = C3_CRYPT_CWLO_KEY128;
195 cw0 = C3_CRYPT_CWLO_KEY192;
202 cw0 = C3_CRYPT_CWLO_KEY256;
207 cw0 |= C3_CRYPT_CWLO_ALG_AES |
212 ses->ses_cw0 = cw0;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/inc/
dmub_srv.h 243 const struct dmub_window *cw0,

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