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    Searched refs:cw1 (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
amdgpu_dmub_dcn20.c 102 const struct dmub_window *cw1)
122 dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
126 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
128 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
amdgpu_dmub_srv.c 341 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; local in function:dmub_srv_hw_init
356 cw1.offset.quad_part = stack_fb->gpu_addr;
357 cw1.region.base = DMUB_CW1_BASE;
358 cw1.region.top = cw1.region.base + stack_fb->size - 1;
368 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
dmub_dcn20.h 168 const struct dmub_window *cw1);
  /src/sys/dev/qbus/
ts.c 423 sc->sc_vts->cmd.cw1 = bp->b_bcount;
427 sc->sc_vts->cmd.cw1 = bp->b_bcount;
431 sc->sc_vts->cmd.cw1 = bp->b_bcount;
435 sc->sc_vts->cmd.cw1 = bp->b_bcount;
465 sc->sc_vts->cmd.cw1 = LOWORD(sc->sc_dmam->dm_segs[0].ds_addr);
519 sc->sc_vts->cmd.cw1 = LOWORD(&sc->sc_bts->chr);
759 sc->sc_vts->cmd.cw1 = 1;
tsreg.h 88 unsigned short cw1; /* low order data pointer address (A15-00) */ member in struct:cmd
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/inc/
dmub_srv.h 244 const struct dmub_window *cw1);

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