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    Searched refs:cw2 (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
amdgpu_dmub_dcn20.c 136 const struct dmub_window *cw2,
147 dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, &offset);
151 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
153 DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
amdgpu_dmub_srv.c 341 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; local in function:dmub_srv_hw_init
376 cw2.offset.quad_part = data_fb->gpu_addr;
377 cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
378 cw2.region.top = cw2.region.base + data_fb->size;
402 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4,
dmub_dcn20.h 171 const struct dmub_window *cw2,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/inc/
dmub_srv.h 247 const struct dmub_window *cw2,
  /src/sys/dev/qbus/
tsreg.h 89 unsigned short cw2; /* high order data pointer address (A21-16) */ member in struct:cmd
ts.c 466 sc->sc_vts->cmd.cw2 = HIWORD(sc->sc_dmam->dm_segs[0].ds_addr);
520 sc->sc_vts->cmd.cw2 = HIWORD(&sc->sc_bts->chr);

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