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    Searched refs:cw3 (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
amdgpu_dmub_dcn20.c 137 const struct dmub_window *cw3,
156 dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);
160 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
162 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
amdgpu_dmub_srv.c 341 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; local in function:dmub_srv_hw_init
380 cw3.offset.quad_part = bios_fb->gpu_addr;
381 cw3.region.base = DMUB_CW3_BASE;
382 cw3.region.top = cw3.region.base + bios_fb->size;
385 cw4.region.base = cw3.region.top + 1;
402 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4,
dmub_dcn20.h 172 const struct dmub_window *cw3,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/inc/
dmub_srv.h 248 const struct dmub_window *cw3,
  /src/sys/dev/qbus/
tsreg.h 90 unsigned short cw3; /* count parameter */ member in struct:cmd
ts.c 467 sc->sc_vts->cmd.cw3 = bp->b_bcount;
521 sc->sc_vts->cmd.cw3 = 010; /* size of charact.-data */

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