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    Searched refs:cw5 (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
amdgpu_dmub_dcn20.c 139 const struct dmub_window *cw5,
174 dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
178 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
180 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
amdgpu_dmub_srv.c 341 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; local in function:dmub_srv_hw_init
391 cw5.offset.quad_part = tracebuff_fb->gpu_addr;
392 cw5.region.base = DMUB_CW5_BASE;
393 cw5.region.top = cw5.region.base + tracebuff_fb->size;
403 &cw5, &cw6);
dmub_dcn20.h 174 const struct dmub_window *cw5,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/inc/
dmub_srv.h 250 const struct dmub_window *cw5,

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