| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| hubp.h | 137 struct dc_plane_dcc_param *dcc,
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| mem_input.h | 159 struct dc_plane_dcc_param *dcc,
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| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_gem_fence_reg.c | 677 u32 dcc = intel_uncore_read(uncore, DCC); local
681 * determined by DCC. For single-channel, neither the CPU
688 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
695 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
702 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
721 if (dcc == 0xffffffff) {
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hubp.c | 172 struct dc_plane_dcc_param *dcc)
185 meta_pitch = dcc->meta_pitch - 1;
187 meta_pitch_c = dcc->meta_pitch_c - 1;
190 meta_pitch = dcc->meta_pitch - 1;
195 if (!dcc->enable) {
534 struct dc_plane_dcc_param *dcc,
538 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
540 hubp1_program_size(hubp, format, plane_size, dcc);
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| dcn10_hubp.h | 697 struct dc_plane_dcc_param *dcc,
718 struct dc_plane_dcc_param *dcc);
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| amdgpu_dcn10_resource.c | 1223 if (!plane->dcc.enable)
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| amdgpu_dcn10_hw_sequencer.c | 2350 &plane_state->dcc,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_hubp.h | 282 struct dc_plane_dcc_param *dcc);
299 struct dc_plane_dcc_param *dcc,
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| amdgpu_dcn20_hubp.c | 333 struct dc_plane_dcc_param *dcc)
349 meta_pitch = dcc->meta_pitch - 1;
351 meta_pitch_c = dcc->meta_pitch_c - 1;
354 meta_pitch = dcc->meta_pitch - 1;
359 if (!dcc->enable) {
527 struct dc_plane_dcc_param *dcc,
533 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
535 hubp2_program_size(hubp, format, plane_size, dcc);
|
| amdgpu_dcn20_resource.c | 1921 pipes[pipe_cnt].pipe.src.dcc = 0;
1939 pipes[pipe_cnt].pipe.src.dcc = false;
2123 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2124 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
2127 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2129 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
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| amdgpu_dcn20_hwseq.c | 1453 &plane_state->dcc,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| display_mode_structs.h | 218 unsigned char dcc; member in struct:_vcs_dpi_display_pipe_source_params_st
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| amdgpu_display_mode_vba.c | 429 ip->dcc_supported : src->dcc && ip->dcc_supported;
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| amdgpu_dml1_display_rq_dlg_calc.c | 1187 dcc_en = e2e_pipe_param.pipe.src.dcc;
1537 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;/* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */
1562 disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; /* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc.c | 1539 if (u->plane_info->dcc.enable != u->surface->dcc.enable
1540 || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1541 || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1873 surface->dcc =
1874 srf_update->plane_info->dcc;
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| amdgpu_dc_debug.c | 162 "plane_state->dcc.enable = %d;\n"
169 plane_state->dcc.enable,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc.h | 750 struct dc_plane_dcc_param dcc; member in struct:dc_plane_state
797 struct dc_plane_dcc_param dcc; member in struct:dc_plane_info
863 * as frame durations and DCC format can also be set.
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 317 * this method requires us to always re-calculate watermark when dcc change
320 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;
323 * allow us to disable dcc on the fly without re-calculating WM
325 * extra overhead for DCC is quite small. for 1080p WM without
326 * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
330 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
334 input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch;
964 * this method requires us to always re-calculate watermark when dcc change
967 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm.c | 3148 struct dc_plane_dcc_param *dcc,
3189 dcc->enable = 1;
3190 dcc->meta_pitch =
3192 dcc->independent_64b_blks = i64b;
3209 struct dc_plane_dcc_param *dcc,
3217 memset(dcc, 0, sizeof(*dcc));
3316 tiling_flags, dcc, address);
3487 &plane_info->dcc, address);
3542 dc_plane_state->dcc = plane_info.dcc
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_mem_input.c | 515 struct dc_plane_dcc_param *dcc,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_mem_input_v.c | 648 struct dc_plane_dcc_param *dcc,
|
