| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| dccg.h | 1 /* $NetBSD: dccg.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */
33 struct dccg { struct
41 void (*update_dpp_dto)(struct dccg *dccg,
44 void (*get_dccg_ref_freq)(struct dccg *dccg,
47 void (*dccg_init)(struct dccg *dccg);
|
| clk_mgr.h | 201 struct dccg;
203 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);
|
| clk_mgr_internal.h | 203 struct dccg *dccg; member in struct:clk_mgr_internal
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| rn_clk_mgr.h | 41 struct dccg *dccg);
|
| amdgpu_rn_clk_mgr.c | 31 #include "dccg.h"
703 struct dccg *dccg)
713 clk_mgr->dccg = dccg;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dccg.c | 37 #define TO_DCN_DCCG(dccg)\
38 container_of(dccg, struct dcn_dccg, base)
50 dccg->ctx->logger
52 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
54 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
56 if (dccg->ref_dppclk && req_dppclk) {
57 int ref_dppclk = dccg->ref_dppclk;
80 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
[all...] |
| dcn20_dccg.h | 31 #include "dccg.h"
96 struct dccg base;
102 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
104 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
108 void dccg2_init(struct dccg *dccg);
110 struct dccg *dccg2_create(
116 void dcn_dccg_destroy(struct dccg **dccg)
[all...] |
| amdgpu_dcn20_hwseq.c | 56 #include "dccg.h"
2299 // Initialize the dccg
2300 if (res_pool->dccg->funcs->dccg_init)
2301 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2306 // Specific to FPGA dccg and registers
|
| amdgpu_dcn20_resource.c | 1415 if (pool->base.dccg != NULL)
1416 dcn_dccg_destroy(&pool->base.dccg);
3588 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3589 if (pool->base.dccg == NULL) {
3590 dm_error("DC: failed to create dccg!\n");
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| dcn20_clk_mgr.h | 31 void dcn2_update_clocks(struct clk_mgr *dccg,
46 struct dccg *dccg);
|
| amdgpu_dcn20_clk_mgr.c | 31 #include "dccg.h"
113 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
126 clk_mgr->dccg->funcs->update_dpp_dto(
127 clk_mgr->dccg, dpp_inst, dppclk_khz);
329 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
438 struct dccg *dccg)
447 clk_mgr->dccg = dccg;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/ |
| dce_clk_mgr.h | 50 int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/ |
| amdgpu_clk_mgr.c | 35 #include "dccg.h"
97 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
150 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
165 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 212 struct dccg *dccg; member in struct:resource_pool
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer.c | 54 #include "dccg.h"
1251 // Initialize the dccg
1252 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
1253 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
1285 if (res_pool->dccg && res_pool->hubbub) {
1287 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
1295 // Not all ASICs have DCCG sw componen
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_hw_sequencer.c | 2433 struct clk_mgr *dccg = dc->clk_mgr; local in function:dce110_prepare_bandwidth
2437 dccg->funcs->update_clocks(
2438 dccg,
2447 struct clk_mgr *dccg = dc->clk_mgr; local in function:dce110_optimize_bandwidth
2451 dccg->funcs->update_clocks(
2452 dccg,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 970 if (pool->base.dccg != NULL)
971 dcn_dccg_destroy(&pool->base.dccg);
1749 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1750 if (pool->base.dccg == NULL) {
1751 dm_error("DC: failed to create dccg!\n");
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc.c | 726 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
|
