HomeSort by: relevance | last modified time | path
    Searched refs:dcefclk (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_smu_v11_0.c 537 smu->smu_table.boot_values.dcefclk = 0;
552 smu->smu_table.boot_values.dcefclk = 0;
599 smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
769 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
783 return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
994 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
1026 pr_err("[%s] failed to get max DCEFCLK from SMC!",
amdgpu_vega20_ppt.c 164 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
824 /* dcefclk */
831 pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
836 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1052 pr_err("Attempt to get current dcefclk Failed!");
1059 pr_err("Attempt to get dcefclk levels Failed!");
1272 pr_err("Failed to set hard min dcefclk !\n");
2259 pr_err("Attempt to set divider for DCEFCLK Failed!");
2264 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
amdgpu_smu.h 217 uint32_t dcefclk; member in struct:smu_bios_boot_up_values

Completed in 18 milliseconds