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    Searched refs:dcfclk (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
clk_mgr.h 85 uint32_t dcfclk; member in struct:clk_state_registers_and_bypass
99 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
105 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass
114 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
121 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
127 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calc_auto.c 1011 v->dcfclk = v->dcfclk_per_state[v->voltage_level];
1231 v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0);
1239 if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
1240 v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency)));
1242 v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
1244 v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
1246 v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0);
1247 if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
1248 v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency)));
1250 v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kby (…)
    [all...]
amdgpu_dcn_calcs.c 120 .round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
482 input.clks_cfg.dcfclk_mhz = v->dcfclk;
566 v->dcfclk = v->dcfclkv_nom0p8;
587 v->dcfclk = v->dcfclkv_max0p9;
607 v->dcfclk = v->dcfclk_per_state[v->voltage_level];
1137 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
1405 /*find that level conresponding dcfclk*/
1597 "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
dcn_calcs.h 215 float dcfclk; member in struct:dcn_bw_internal_vars
576 int round_trip_ping_latency_cycles; /*DCFCLK Cycles*/
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
amdgpu_rn_clk_mgr.c 263 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
289 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
290 regs_and_bypass->dcfclk,
324 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
429 /* dcfclk wil be used to select WM*/

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