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    Searched refs:dcn (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_debug.c 357 context->bw_ctx.bw.dcn.clk.dispclk_khz,
358 context->bw_ctx.bw.dcn.clk.dppclk_khz,
359 context->bw_ctx.bw.dcn.clk.dcfclk_khz,
360 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
361 context->bw_ctx.bw.dcn.clk.fclk_khz,
362 context->bw_ctx.bw.dcn.clk.socclk_khz);
365 context->bw_ctx.bw.dcn.clk.dispclk_khz,
366 context->bw_ctx.bw.dcn.clk.dppclk_khz,
367 context->bw_ctx.bw.dcn.clk.dcfclk_khz,
368 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz
    [all...]
amdgpu_dc.c 1793 if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
1796 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2693 info->displayClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
2694 info->engineClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
2695 info->memoryClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
2696 info->maxSupportedDppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
2697 info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
2698 info->socClock = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
2699 info->dcfClockDeepSleep = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
2700 info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 297 /* Unsupported swizzle modes for dcn */
555 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
557 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
559 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
561 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
562 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
569 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
571 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
573 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
575 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 72 #include "dcn/dcn_2_0_0_offset.h"
73 #include "dcn/dcn_2_0_0_sh_mask.h"
376 /* DCN */
2254 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2728 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2729 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2730 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2731 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2732 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2733 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_ (…)
    [all...]
amdgpu_dcn20_hwseq.c 1643 * is unsupported on DCN.
1677 &context->bw_ctx.bw.dcn.watermarks,
1690 &context->bw_ctx.bw.dcn.watermarks,
1771 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
amdgpu_dcn20_clk_mgr.c 41 #include "dcn/dcn_2_0_0_offset.h"
42 #include "dcn/dcn_2_0_0_sh_mask.h"
156 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
263 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
282 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
388 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
391 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
394 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
397 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer_debug.c 480 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
481 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
482 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
483 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
484 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
485 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
amdgpu_dcn10_hw_sequencer.c 356 * TODO: Implement DCN-specific read_otg_state hooks.
453 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
454 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
455 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
456 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
457 dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
458 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
459 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
731 /* initialize dcn global */
736 /* initialize dcn per pipe *
    [all...]
  /src/sys/dev/ic/
uhareg.h 199 u_char dcn:1; /* disable disconnect for this command */ member in struct:uha_mscp
uha.c 453 mscp->dcn = 0x00;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
amdgpu_rv1_clk_mgr.c 137 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 344 struct dcn_bw_output dcn; member in union:bw_output
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_resource.c 76 #include "dcn/dcn_2_1_0_offset.h"
77 #include "dcn/dcn_2_1_0_sh_mask.h"
287 /* DCN */
1108 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1113 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1118 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1124 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
amdgpu_rn_clk_mgr.c 61 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
106 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
188 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

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