| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_i2c.c | 35 struct ddc *ddc,
41 if (!ddc) {
51 dce_i2c_hw = acquire_i2c_hw_engine(pool, ddc);
54 return dce_i2c_submit_command_hw(pool, ddc, cmd, dce_i2c_hw);
56 dce_i2c_sw.ctx = ddc->ctx;
57 if (dce_i2c_engine_acquire_sw(&dce_i2c_sw, ddc)) {
58 return dce_i2c_submit_command_sw(pool, ddc, cmd, &dce_i2c_sw);
|
| dce_i2c.h | 37 struct ddc *ddc,
|
| dce_i2c_sw.h | 38 struct ddc *ddc; member in struct:dce_i2c_sw
50 struct ddc *ddc,
56 struct ddc *ddc_handle);
|
| amdgpu_dce_i2c_sw.c | 47 struct ddc *ddc,
53 dal_gpio_get_value(ddc->pin_data, &value);
55 dal_gpio_get_value(ddc->pin_clock, &value);
61 struct ddc *ddc,
68 dal_gpio_set_value(ddc->pin_data, value);
70 dal_gpio_set_value(ddc->pin_clock, value);
77 dal_ddc_close(dce_i2c_sw->ddc);
78 dce_i2c_sw->ddc = NULL
409 struct ddc *ddc = engine->ddc; local in function:dce_i2c_sw_engine_submit_channel_request
[all...] |
| amdgpu_dce_aux.c | 82 dal_ddc_close(engine->ddc);
84 engine->ddc = NULL;
275 EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE,
404 struct ddc *ddc)
411 result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
418 dal_ddc_close(ddc);
422 engine->ddc = ddc;
437 static uint32_t dce_aux_configure_timeout(struct ddc_service *ddc,
[all...] |
| amdgpu_dce_i2c_hw.c | 227 * for reading DDC/EDID information is 0b1010001.
375 struct ddc *ddc)
381 if (!ddc)
384 if (ddc->hw_info.hw_supported) {
385 enum gpio_ddc_line line = dal_ddc_get_line(ddc);
398 result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
414 dce_i2c_hw->ddc = ddc;
563 struct ddc *ddc
[all...] |
| dce_i2c_hw.h | 260 struct ddc *ddc; member in struct:dce_i2c_hw
320 struct ddc *ddc,
326 struct ddc *ddc);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| dc_link_ddc.h | 78 void dal_ddc_service_destroy(struct ddc_service **ddc);
80 enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc);
83 struct ddc_service *ddc,
86 bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc);
89 struct ddc_service *ddc,
93 struct ddc_service *ddc,
100 bool dal_ddc_submit_aux_command(struct ddc_service *ddc,
103 int dc_link_aux_transfer_raw(struct ddc_service *ddc,
107 bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
110 uint32_t dc_link_aux_configure_timeout(struct ddc_service *ddc,
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/include/ |
| gpio_service_interface.h | 73 struct ddc *dal_gpio_create_ddc(
80 struct ddc **ddc);
105 struct ddc *ddc,
110 struct ddc *ddc,
114 const struct ddc *ddc);
117 struct ddc *ddc
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_event_log.h | 40 #define EVENT_LOG_AUX_REQ(ddc, type, action, address, len, data) \
41 (void)((void)(ddc), (void)(type), (void)(action), (void)(address), \
43 #define EVENT_LOG_AUX_REP(ddc, type, replyStatus, len, data) \
44 (void)((void)(ddc), (void)(type), (void)(replyStatus), (void)(len), \
|
| dc_ddc_types.h | 121 struct ddc { struct
166 struct ddc *ddc_pin;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| amdgpu_gpio_service.c | 473 struct ddc *dal_gpio_create_ddc(
481 struct ddc *ddc; local in function:dal_gpio_create_ddc
486 ddc = kzalloc(sizeof(struct ddc), GFP_KERNEL);
488 if (!ddc) {
493 ddc->pin_data = dal_gpio_create(
496 if (!ddc->pin_data) {
501 ddc->pin_clock = dal_gpio_create(
504 if (!ddc->pin_clock)
[all...] |
| amdgpu_hw_ddc.c | 47 ddc->shifts->field_name, ddc->masks->field_name
50 ddc->base.base.ctx
52 (ddc->regs->reg)
78 struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr); local in function:set_config
85 hw_gpio = &ddc->base;
97 switch (config_data->config.ddc.type) {
145 if (config_data->config.ddc.data_en_bit_present ||
146 config_data->config.ddc.clock_en_bit_present)
158 if (ddc->regs->dc_gpio_aux_ctrl_5 != 0)
[all...] |
| amdgpu_gpio_base.c | 76 if (!gpio->hw_container.ddc) {
245 return gpio->hw_container.ddc;
297 gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en);
300 gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en);
331 kfree((*gpio)->hw_container.ddc);
332 (*gpio)->hw_container.ddc = NULL;
336 kfree((*gpio)->hw_container.ddc);
337 (*gpio)->hw_container.ddc = NULL;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_ddc.c | 251 static void ddc_service_destruct(struct ddc_service *ddc)
253 if (ddc->ddc_pin)
254 dal_gpio_destroy_ddc(&ddc->ddc_pin);
257 void dal_ddc_service_destroy(struct ddc_service **ddc)
259 if (!ddc || !*ddc) {
263 ddc_service_destruct(*ddc);
264 kfree(*ddc);
265 *ddc = NULL;
268 enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce110/ |
| amdgpu_hw_factory_dce110.c | 125 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); local in function:define_ddc_registers
129 ddc->regs = &ddc_data_regs[en];
130 ddc->base.regs = &ddc_data_regs[en].gpio;
133 ddc->regs = &ddc_clk_regs[en];
134 ddc->base.regs = &ddc_clk_regs[en].gpio;
141 ddc->shifts = &ddc_shift;
142 ddc->masks = &ddc_mask;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce80/ |
| amdgpu_hw_factory_dce80.c | 125 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); local in function:define_ddc_registers
129 ddc->regs = &ddc_data_regs[en];
130 ddc->base.regs = &ddc_data_regs[en].gpio;
133 ddc->regs = &ddc_clk_regs[en];
134 ddc->base.regs = &ddc_clk_regs[en].gpio;
141 ddc->shifts = &ddc_shift;
142 ddc->masks = &ddc_mask;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| aux_engine.h | 88 struct ddc *ddc; member in struct:aux_engine
146 struct ddc_service *ddc,
175 struct ddc *ddc);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/ |
| amdgpu_hw_factory_dce120.c | 138 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); local in function:define_ddc_registers
142 ddc->regs = &ddc_data_regs[en];
143 ddc->base.regs = &ddc_data_regs[en].gpio;
146 ddc->regs = &ddc_clk_regs[en];
147 ddc->base.regs = &ddc_clk_regs[en].gpio;
154 ddc->shifts = &ddc_shift;
155 ddc->masks = &ddc_mask;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/ |
| amdgpu_hw_factory_dcn10.c | 170 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); local in function:define_ddc_registers
174 ddc->regs = &ddc_data_regs[en];
175 ddc->base.regs = &ddc_data_regs[en].gpio;
178 ddc->regs = &ddc_clk_regs[en];
179 ddc->base.regs = &ddc_clk_regs[en].gpio;
186 ddc->shifts = &ddc_shift;
187 ddc->masks = &ddc_mask;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/ |
| amdgpu_hw_factory_dcn20.c | 188 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); local in function:define_ddc_registers
192 ddc->regs = &ddc_data_regs_dcn[en];
193 ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
196 ddc->regs = &ddc_clk_regs_dcn[en];
197 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
204 ddc->shifts = &ddc_shift[en];
205 ddc->masks = &ddc_mask[en];
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/ |
| amdgpu_hw_factory_dcn21.c | 178 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); local in function:define_ddc_registers
182 ddc->regs = &ddc_data_regs_dcn[en];
183 ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
186 ddc->regs = &ddc_clk_regs_dcn[en];
187 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
194 ddc->shifts = &ddc_shift[en];
195 ddc->masks = &ddc_mask[en];
|
| /src/sys/dev/fdt/ |
| hdmi_connector.c | 57 i2c_tag_t ddc; member in struct:dispcon_hdmi_connector
121 if (hdmi_connector->ddc != NULL) {
124 error = ddc_read_edid_block(hdmi_connector->ddc,
208 hdmi_connector->ddc = fdtbus_i2c_acquire(phandle, "ddc-i2c-bus");
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx6q-skov-revc-lt2.dts | 16 ddc-i2c-bus = <&i2c2>;
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/ |
| sun50i-h6-pine-h64-model-b.dts | 22 /delete-property/ ddc-en-gpios;
|
