| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/ |
| bcm958742t.dts | 47 mmc-ddr-1_8v;
|
| bcm958742k.dts | 47 mmc-ddr-1_8v;
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| imx8-ss-ddr.dtsi | 13 ddr-pmu@5c020000 {
14 compatible = "fsl,imx8-ddr-pmu";
|
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/qca/ |
| ar9132.dtsi | 28 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
52 compatible = "qca,ar9132-ddr-controller",
53 "qca,ar7240-ddr-controller";
56 #qca,ddr-wb-channel-cells = <1>;
98 clock-output-names = "cpu", "ddr", "ahb";
|
| ar9331.dtsi | 28 qca,ddr-wb-channel-interrupts = <2>, <3>;
29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
56 compatible = "qca,ar7240-ddr-controller";
59 #qca,ddr-wb-channel-cells = <1>;
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| bcm7445.dtsi | 239 memc-ddr@2000 {
240 compatible = "brcm,brcmstb-memc-ddr";
244 ddr-phy@6000 {
245 compatible = "brcm,brcmstb-ddr-phy-v240.1";
250 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
261 memc-ddr@2000 {
262 compatible = "brcm,brcmstb-memc-ddr";
266 ddr-phy@6000 {
267 compatible = "brcm,brcmstb-ddr-phy-v240.1";
272 compatible = "brcm,brcmstb-ddr-shimphy-v1.0"
[all...] |
| exynos5260-xyref5260.dts | 73 samsung,dw-mshc-ddr-timing = <0 2>;
85 samsung,dw-mshc-ddr-timing = <1 2>;
|
| stm32mp157a-icore-stm32mp1.dtsi | 90 vdd_ddr: regulator-vdd-ddr {
98 vtt_ddr: regulator-vtt-ddr {
107 vref_ddr: regulator-vref-ddr {
|
| rk3228-evb.dts | 33 mmc-ddr-1_8v;
|
| exynos5410-smdk5410.dts | 53 samsung,dw-mshc-ddr-timing = <1 2>;
63 samsung,dw-mshc-ddr-timing = <1 2>;
|
| ecx-2000.dts | 77 compatible = "calxeda,ecx-2000-ddr-ctrl";
|
| highbank.dts | 108 compatible = "calxeda,hb-ddr-ctrl";
|
| keystone-k2e-clocks.dtsi | 30 clock-output-names = "ddr-3a-pll-clk";
|
| tegra30-cardhu-a04.dts | 21 regulator-name = "ddr";
|
| stm32mp157a-microgea-stm32mp1.dtsi | 84 vddq_ddr: regulator-vddq-ddr {
|
| /src/sys/dev/sdmmc/ |
| sdmmcchip.h | 87 #define sdmmc_chip_bus_clock(tag, handle, freq, ddr) \
88 ((tag)->bus_clock_ddr ? (tag)->bus_clock_ddr((handle), (freq), (ddr)) : ((ddr) ? EINVAL : ((tag)->bus_clock((handle), (freq)))))
|
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/brcm/ |
| bcm7425.dtsi | 544 memc-ddr@2000 {
545 compatible = "brcm,brcmstb-memc-ddr";
549 ddr-phy@6000 {
550 compatible = "brcm,brcmstb-ddr-phy";
555 compatible = "brcm,brcmstb-ddr-shimphy";
571 memc-ddr@2000 {
572 compatible = "brcm,brcmstb-memc-ddr";
576 ddr-phy@6000 {
577 compatible = "brcm,brcmstb-ddr-phy";
582 compatible = "brcm,brcmstb-ddr-shimphy"
[all...] |
| bcm7435.dtsi | 559 memc-ddr@2000 {
560 compatible = "brcm,brcmstb-memc-ddr";
564 ddr-phy@6000 {
565 compatible = "brcm,brcmstb-ddr-phy";
570 compatible = "brcm,brcmstb-ddr-shimphy";
586 memc-ddr@2000 {
587 compatible = "brcm,brcmstb-memc-ddr";
591 ddr-phy@6000 {
592 compatible = "brcm,brcmstb-ddr-phy";
597 compatible = "brcm,brcmstb-ddr-shimphy"
[all...] |
| bcm7360.dtsi | 452 memc-ddr@2000 {
453 compatible = "brcm,brcmstb-memc-ddr";
457 ddr-phy@6000 {
458 compatible = "brcm,brcmstb-ddr-phy";
463 compatible = "brcm,brcmstb-ddr-shimphy";
|
| bcm7362.dtsi | 448 memc-ddr@2000 {
449 compatible = "brcm,brcmstb-memc-ddr";
453 ddr-phy@6000 {
454 compatible = "brcm,brcmstb-ddr-phy";
459 compatible = "brcm,brcmstb-ddr-shimphy";
|
| bcm7346.dtsi | 533 memc-ddr@2000 {
534 compatible = "brcm,brcmstb-memc-ddr";
538 ddr-phy@6000 {
539 compatible = "brcm,brcmstb-ddr-phy";
544 compatible = "brcm,brcmstb-ddr-shimphy";
|
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/microchip/ |
| mpfs-polarberry.dts | 66 mmc-ddr-1_8v;
|
| mpfs-sev-kit.dts | 99 mmc-ddr-1_8v;
|
| /src/sys/arch/arm/rockchip/ |
| rk_gpio.c | 242 uint32_t ddr; local in function:rk_gpio_pin_ctl
247 ddr = RD4(sc, GPIO_SWPORTA_DDR_REG);
249 ddr &= ~__BIT(pin);
251 ddr |= __BIT(pin);
252 WR4(sc, GPIO_SWPORTA_DDR_REG, ddr);
293 uint32_t ddr; local in function:rk_gpio_v2_pin_ctl
298 ddr = (flags & GPIO_PIN_OUTPUT) ? GPIOV2_DATA_MASK(pin) : 0;
299 WR4(sc, GPIOV2_SWPORT_DDR_REG(pin), GPIOV2_WRITE_MASK(pin) | ddr);
|
| /src/sys/arch/hpcsh/dev/ |
| j6x0lcd.c | 181 uint8_t dcr, ddr; local in function:j6x0lcd_attach
196 ddr = DAC_(DR0);
197 sc->sc_brightness = J6X0LCD_DA_TO_BRIGHTNESS(ddr);
|
