1 /* $NetBSD: opregion.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $ */ 2 3 /* 4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: opregion.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $"); 28 29 #include <linux/acpi.h> 30 #include "i915_drv.h" 31 #include "gvt.h" 32 33 /* 34 * Note: Only for GVT-g virtual VBT generation, other usage must 35 * not do like this. 36 */ 37 #define _INTEL_BIOS_PRIVATE 38 #include "display/intel_vbt_defs.h" 39 40 #define OPREGION_SIGNATURE "IntelGraphicsMem" 41 #define MBOX_VBT (1<<3) 42 43 /* device handle */ 44 #define DEVICE_TYPE_CRT 0x01 45 #define DEVICE_TYPE_EFP1 0x04 46 #define DEVICE_TYPE_EFP2 0x40 47 #define DEVICE_TYPE_EFP3 0x20 48 #define DEVICE_TYPE_EFP4 0x10 49 50 struct opregion_header { 51 u8 signature[16]; 52 u32 size; 53 u32 opregion_ver; 54 u8 bios_ver[32]; 55 u8 vbios_ver[16]; 56 u8 driver_ver[16]; 57 u32 mboxes; 58 u32 driver_model; 59 u32 pcon; 60 u8 dver[32]; 61 u8 rsvd[124]; 62 } __packed; 63 64 struct bdb_data_header { 65 u8 id; 66 u16 size; /* data size */ 67 } __packed; 68 69 /* For supporting windows guest with opregion, here hardcode the emulated 70 * bdb header version as '186', and the corresponding child_device_config 71 * length should be '33' but not '38'. 72 */ 73 struct efp_child_device_config { 74 u16 handle; 75 u16 device_type; 76 u16 device_class; 77 u8 i2c_speed; 78 u8 dp_onboard_redriver; /* 158 */ 79 u8 dp_ondock_redriver; /* 158 */ 80 u8 hdmi_level_shifter_value:4; /* 169 */ 81 u8 hdmi_max_data_rate:4; /* 204 */ 82 u16 dtd_buf_ptr; /* 161 */ 83 u8 edidless_efp:1; /* 161 */ 84 u8 compression_enable:1; /* 198 */ 85 u8 compression_method:1; /* 198 */ 86 u8 ganged_edp:1; /* 202 */ 87 u8 skip0:4; 88 u8 compression_structure_index:4; /* 198 */ 89 u8 skip1:4; 90 u8 slave_port; /* 202 */ 91 u8 skip2; 92 u8 dvo_port; 93 u8 i2c_pin; /* for add-in card */ 94 u8 slave_addr; /* for add-in card */ 95 u8 ddc_pin; 96 u16 edid_ptr; 97 u8 dvo_config; 98 u8 efp_docked_port:1; /* 158 */ 99 u8 lane_reversal:1; /* 184 */ 100 u8 onboard_lspcon:1; /* 192 */ 101 u8 iboost_enable:1; /* 196 */ 102 u8 hpd_invert:1; /* BXT 196 */ 103 u8 slip3:3; 104 u8 hdmi_compat:1; 105 u8 dp_compat:1; 106 u8 tmds_compat:1; 107 u8 skip4:5; 108 u8 aux_channel; 109 u8 dongle_detect; 110 u8 pipe_cap:2; 111 u8 sdvo_stall:1; /* 158 */ 112 u8 hpd_status:2; 113 u8 integrated_encoder:1; 114 u8 skip5:2; 115 u8 dvo_wiring; 116 u8 mipi_bridge_type; /* 171 */ 117 u16 device_class_ext; 118 u8 dvo_function; 119 } __packed; 120 121 struct vbt { 122 /* header->bdb_offset point to bdb_header offset */ 123 struct vbt_header header; 124 struct bdb_header bdb_header; 125 126 struct bdb_data_header general_features_header; 127 struct bdb_general_features general_features; 128 129 struct bdb_data_header general_definitions_header; 130 struct bdb_general_definitions general_definitions; 131 132 struct efp_child_device_config child0; 133 struct efp_child_device_config child1; 134 struct efp_child_device_config child2; 135 struct efp_child_device_config child3; 136 137 struct bdb_data_header driver_features_header; 138 struct bdb_driver_features driver_features; 139 }; 140 141 static void virt_vbt_generation(struct vbt *v) 142 { 143 int num_child; 144 145 memset(v, 0, sizeof(struct vbt)); 146 147 v->header.signature[0] = '$'; 148 v->header.signature[1] = 'V'; 149 v->header.signature[2] = 'B'; 150 v->header.signature[3] = 'T'; 151 152 /* there's features depending on version! */ 153 v->header.version = 155; 154 v->header.header_size = sizeof(v->header); 155 v->header.vbt_size = sizeof(struct vbt) - sizeof(v->header); 156 v->header.bdb_offset = offsetof(struct vbt, bdb_header); 157 158 strcpy(&v->bdb_header.signature[0], "BIOS_DATA_BLOCK"); 159 v->bdb_header.version = 186; /* child_dev_size = 33 */ 160 v->bdb_header.header_size = sizeof(v->bdb_header); 161 162 v->bdb_header.bdb_size = sizeof(struct vbt) - sizeof(struct vbt_header) 163 - sizeof(struct bdb_header); 164 165 /* general features */ 166 v->general_features_header.id = BDB_GENERAL_FEATURES; 167 v->general_features_header.size = sizeof(struct bdb_general_features); 168 v->general_features.int_crt_support = 0; 169 v->general_features.int_tv_support = 0; 170 171 /* child device */ 172 num_child = 4; /* each port has one child */ 173 v->general_definitions.child_dev_size = 174 sizeof(struct efp_child_device_config); 175 v->general_definitions_header.id = BDB_GENERAL_DEFINITIONS; 176 /* size will include child devices */ 177 v->general_definitions_header.size = 178 sizeof(struct bdb_general_definitions) + 179 num_child * v->general_definitions.child_dev_size; 180 181 /* portA */ 182 v->child0.handle = DEVICE_TYPE_EFP1; 183 v->child0.device_type = DEVICE_TYPE_DP; 184 v->child0.dvo_port = DVO_PORT_DPA; 185 v->child0.aux_channel = DP_AUX_A; 186 v->child0.dp_compat = true; 187 v->child0.integrated_encoder = true; 188 189 /* portB */ 190 v->child1.handle = DEVICE_TYPE_EFP2; 191 v->child1.device_type = DEVICE_TYPE_DP; 192 v->child1.dvo_port = DVO_PORT_DPB; 193 v->child1.aux_channel = DP_AUX_B; 194 v->child1.dp_compat = true; 195 v->child1.integrated_encoder = true; 196 197 /* portC */ 198 v->child2.handle = DEVICE_TYPE_EFP3; 199 v->child2.device_type = DEVICE_TYPE_DP; 200 v->child2.dvo_port = DVO_PORT_DPC; 201 v->child2.aux_channel = DP_AUX_C; 202 v->child2.dp_compat = true; 203 v->child2.integrated_encoder = true; 204 205 /* portD */ 206 v->child3.handle = DEVICE_TYPE_EFP4; 207 v->child3.device_type = DEVICE_TYPE_DP; 208 v->child3.dvo_port = DVO_PORT_DPD; 209 v->child3.aux_channel = DP_AUX_D; 210 v->child3.dp_compat = true; 211 v->child3.integrated_encoder = true; 212 213 /* driver features */ 214 v->driver_features_header.id = BDB_DRIVER_FEATURES; 215 v->driver_features_header.size = sizeof(struct bdb_driver_features); 216 v->driver_features.lvds_config = BDB_DRIVER_FEATURE_NO_LVDS; 217 } 218 219 /** 220 * intel_vgpu_init_opregion - initialize the stuff used to emulate opregion 221 * @vgpu: a vGPU 222 * 223 * Returns: 224 * Zero on success, negative error code if failed. 225 */ 226 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu) 227 { 228 u8 *buf; 229 struct opregion_header *header; 230 struct vbt v; 231 const char opregion_signature[16] = OPREGION_SIGNATURE; 232 233 gvt_dbg_core("init vgpu%d opregion\n", vgpu->id); 234 vgpu_opregion(vgpu)->va = (void *)__get_free_pages(GFP_KERNEL | 235 __GFP_ZERO, 236 get_order(INTEL_GVT_OPREGION_SIZE)); 237 if (!vgpu_opregion(vgpu)->va) { 238 gvt_err("fail to get memory for vgpu virt opregion\n"); 239 return -ENOMEM; 240 } 241 242 /* emulated opregion with VBT mailbox only */ 243 buf = (u8 *)vgpu_opregion(vgpu)->va; 244 header = (struct opregion_header *)buf; 245 memcpy(header->signature, opregion_signature, 246 sizeof(opregion_signature)); 247 header->size = 0x8; 248 header->opregion_ver = 0x02000000; 249 header->mboxes = MBOX_VBT; 250 251 /* for unknown reason, the value in LID field is incorrect 252 * which block the windows guest, so workaround it by force 253 * setting it to "OPEN" 254 */ 255 buf[INTEL_GVT_OPREGION_CLID] = 0x3; 256 257 /* emulated vbt from virt vbt generation */ 258 virt_vbt_generation(&v); 259 memcpy(buf + INTEL_GVT_OPREGION_VBT_OFFSET, &v, sizeof(struct vbt)); 260 261 return 0; 262 } 263 264 static int map_vgpu_opregion(struct intel_vgpu *vgpu, bool map) 265 { 266 u64 mfn; 267 int i, ret; 268 269 for (i = 0; i < INTEL_GVT_OPREGION_PAGES; i++) { 270 mfn = intel_gvt_hypervisor_virt_to_mfn(vgpu_opregion(vgpu)->va 271 + i * PAGE_SIZE); 272 if (mfn == INTEL_GVT_INVALID_ADDR) { 273 gvt_vgpu_err("fail to get MFN from VA\n"); 274 return -EINVAL; 275 } 276 ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, 277 vgpu_opregion(vgpu)->gfn[i], 278 mfn, 1, map); 279 if (ret) { 280 gvt_vgpu_err("fail to map GFN to MFN, errno: %d\n", 281 ret); 282 return ret; 283 } 284 } 285 286 vgpu_opregion(vgpu)->mapped = map; 287 288 return 0; 289 } 290 291 /** 292 * intel_vgpu_opregion_base_write_handler - Opregion base register write handler 293 * 294 * @vgpu: a vGPU 295 * @gpa: guest physical address of opregion 296 * 297 * Returns: 298 * Zero on success, negative error code if failed. 299 */ 300 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa) 301 { 302 303 int i, ret = 0; 304 305 gvt_dbg_core("emulate opregion from kernel\n"); 306 307 switch (intel_gvt_host.hypervisor_type) { 308 case INTEL_GVT_HYPERVISOR_KVM: 309 for (i = 0; i < INTEL_GVT_OPREGION_PAGES; i++) 310 vgpu_opregion(vgpu)->gfn[i] = (gpa >> PAGE_SHIFT) + i; 311 break; 312 case INTEL_GVT_HYPERVISOR_XEN: 313 /** 314 * Wins guest on Xengt will write this register twice: xen 315 * hvmloader and windows graphic driver. 316 */ 317 if (vgpu_opregion(vgpu)->mapped) 318 map_vgpu_opregion(vgpu, false); 319 320 for (i = 0; i < INTEL_GVT_OPREGION_PAGES; i++) 321 vgpu_opregion(vgpu)->gfn[i] = (gpa >> PAGE_SHIFT) + i; 322 323 ret = map_vgpu_opregion(vgpu, true); 324 break; 325 default: 326 ret = -EINVAL; 327 gvt_vgpu_err("not supported hypervisor\n"); 328 } 329 330 return ret; 331 } 332 333 /** 334 * intel_vgpu_clean_opregion - clean the stuff used to emulate opregion 335 * @vgpu: a vGPU 336 * 337 */ 338 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu) 339 { 340 gvt_dbg_core("vgpu%d: clean vgpu opregion\n", vgpu->id); 341 342 if (!vgpu_opregion(vgpu)->va) 343 return; 344 345 if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_XEN) { 346 if (vgpu_opregion(vgpu)->mapped) 347 map_vgpu_opregion(vgpu, false); 348 } else if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_KVM) { 349 /* Guest opregion is released by VFIO */ 350 } 351 free_pages((unsigned long)vgpu_opregion(vgpu)->va, 352 get_order(INTEL_GVT_OPREGION_SIZE)); 353 354 vgpu_opregion(vgpu)->va = NULL; 355 356 } 357 358 359 #define GVT_OPREGION_FUNC(scic) \ 360 ({ \ 361 u32 __ret; \ 362 __ret = (scic & OPREGION_SCIC_FUNC_MASK) >> \ 363 OPREGION_SCIC_FUNC_SHIFT; \ 364 __ret; \ 365 }) 366 367 #define GVT_OPREGION_SUBFUNC(scic) \ 368 ({ \ 369 u32 __ret; \ 370 __ret = (scic & OPREGION_SCIC_SUBFUNC_MASK) >> \ 371 OPREGION_SCIC_SUBFUNC_SHIFT; \ 372 __ret; \ 373 }) 374 375 static const char *opregion_func_name(u32 func) 376 { 377 const char *name = NULL; 378 379 switch (func) { 380 case 0 ... 3: 381 case 5: 382 case 7 ... 15: 383 name = "Reserved"; 384 break; 385 386 case 4: 387 name = "Get BIOS Data"; 388 break; 389 390 case 6: 391 name = "System BIOS Callbacks"; 392 break; 393 394 default: 395 name = "Unknown"; 396 break; 397 } 398 return name; 399 } 400 401 static const char *opregion_subfunc_name(u32 subfunc) 402 { 403 const char *name = NULL; 404 405 switch (subfunc) { 406 case 0: 407 name = "Supported Calls"; 408 break; 409 410 case 1: 411 name = "Requested Callbacks"; 412 break; 413 414 case 2 ... 3: 415 case 8 ... 9: 416 name = "Reserved"; 417 break; 418 419 case 5: 420 name = "Boot Display"; 421 break; 422 423 case 6: 424 name = "TV-Standard/Video-Connector"; 425 break; 426 427 case 7: 428 name = "Internal Graphics"; 429 break; 430 431 case 10: 432 name = "Spread Spectrum Clocks"; 433 break; 434 435 case 11: 436 name = "Get AKSV"; 437 break; 438 439 default: 440 name = "Unknown"; 441 break; 442 } 443 return name; 444 }; 445 446 static bool querying_capabilities(u32 scic) 447 { 448 u32 func, subfunc; 449 450 func = GVT_OPREGION_FUNC(scic); 451 subfunc = GVT_OPREGION_SUBFUNC(scic); 452 453 if ((func == INTEL_GVT_OPREGION_SCIC_F_GETBIOSDATA && 454 subfunc == INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS) 455 || (func == INTEL_GVT_OPREGION_SCIC_F_GETBIOSDATA && 456 subfunc == INTEL_GVT_OPREGION_SCIC_SF_REQEUSTEDCALLBACKS) 457 || (func == INTEL_GVT_OPREGION_SCIC_F_GETBIOSCALLBACKS && 458 subfunc == INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS)) { 459 return true; 460 } 461 return false; 462 } 463 464 /** 465 * intel_vgpu_emulate_opregion_request - emulating OpRegion request 466 * @vgpu: a vGPU 467 * @swsci: SWSCI request 468 * 469 * Returns: 470 * Zero on success, negative error code if failed 471 */ 472 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci) 473 { 474 u32 scic, parm; 475 u32 func, subfunc; 476 u64 scic_pa = 0, parm_pa = 0; 477 int ret; 478 479 switch (intel_gvt_host.hypervisor_type) { 480 case INTEL_GVT_HYPERVISOR_XEN: 481 scic = *((u32 *)vgpu_opregion(vgpu)->va + 482 INTEL_GVT_OPREGION_SCIC); 483 parm = *((u32 *)vgpu_opregion(vgpu)->va + 484 INTEL_GVT_OPREGION_PARM); 485 break; 486 case INTEL_GVT_HYPERVISOR_KVM: 487 scic_pa = (vgpu_opregion(vgpu)->gfn[0] << PAGE_SHIFT) + 488 INTEL_GVT_OPREGION_SCIC; 489 parm_pa = (vgpu_opregion(vgpu)->gfn[0] << PAGE_SHIFT) + 490 INTEL_GVT_OPREGION_PARM; 491 492 ret = intel_gvt_hypervisor_read_gpa(vgpu, scic_pa, 493 &scic, sizeof(scic)); 494 if (ret) { 495 gvt_vgpu_err("guest opregion read error %d, gpa 0x%llx, len %lu\n", 496 ret, scic_pa, sizeof(scic)); 497 return ret; 498 } 499 500 ret = intel_gvt_hypervisor_read_gpa(vgpu, parm_pa, 501 &parm, sizeof(parm)); 502 if (ret) { 503 gvt_vgpu_err("guest opregion read error %d, gpa 0x%llx, len %lu\n", 504 ret, scic_pa, sizeof(scic)); 505 return ret; 506 } 507 508 break; 509 default: 510 gvt_vgpu_err("not supported hypervisor\n"); 511 return -EINVAL; 512 } 513 514 if (!(swsci & SWSCI_SCI_SELECT)) { 515 gvt_vgpu_err("requesting SMI service\n"); 516 return 0; 517 } 518 /* ignore non 0->1 trasitions */ 519 if ((vgpu_cfg_space(vgpu)[INTEL_GVT_PCI_SWSCI] 520 & SWSCI_SCI_TRIGGER) || 521 !(swsci & SWSCI_SCI_TRIGGER)) { 522 return 0; 523 } 524 525 func = GVT_OPREGION_FUNC(scic); 526 subfunc = GVT_OPREGION_SUBFUNC(scic); 527 if (!querying_capabilities(scic)) { 528 gvt_vgpu_err("requesting runtime service: func \"%s\"," 529 " subfunc \"%s\"\n", 530 opregion_func_name(func), 531 opregion_subfunc_name(subfunc)); 532 /* 533 * emulate exit status of function call, '0' means 534 * "failure, generic, unsupported or unknown cause" 535 */ 536 scic &= ~OPREGION_SCIC_EXIT_MASK; 537 goto out; 538 } 539 540 scic = 0; 541 parm = 0; 542 543 out: 544 switch (intel_gvt_host.hypervisor_type) { 545 case INTEL_GVT_HYPERVISOR_XEN: 546 *((u32 *)vgpu_opregion(vgpu)->va + 547 INTEL_GVT_OPREGION_SCIC) = scic; 548 *((u32 *)vgpu_opregion(vgpu)->va + 549 INTEL_GVT_OPREGION_PARM) = parm; 550 break; 551 case INTEL_GVT_HYPERVISOR_KVM: 552 ret = intel_gvt_hypervisor_write_gpa(vgpu, scic_pa, 553 &scic, sizeof(scic)); 554 if (ret) { 555 gvt_vgpu_err("guest opregion write error %d, gpa 0x%llx, len %lu\n", 556 ret, scic_pa, sizeof(scic)); 557 return ret; 558 } 559 560 ret = intel_gvt_hypervisor_write_gpa(vgpu, parm_pa, 561 &parm, sizeof(parm)); 562 if (ret) { 563 gvt_vgpu_err("guest opregion write error %d, gpa 0x%llx, len %lu\n", 564 ret, scic_pa, sizeof(scic)); 565 return ret; 566 } 567 568 break; 569 default: 570 gvt_vgpu_err("not supported hypervisor\n"); 571 return -EINVAL; 572 } 573 574 return 0; 575 } 576
Indexes created Sat Sep 20 22:09:52 GMT 2025