| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| atombios_crtc.h | 41 u32 dispclk);
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| amdgpu_atombios_crtc.c | 478 u32 dispclk)
499 args.v5.usPixelClock = cpu_to_le16(dispclk);
506 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| clk_mgr.h | 89 uint32_t dispclk; member in struct:clk_state_registers_and_bypass
103 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
107 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass
111 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
118 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
131 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| dce_calcs.h | 334 struct bw_fixed dispclk; member in struct:bw_calcs_data
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| dcn_calcs.h | 437 float dispclk; member in struct:dcn_bw_internal_vars
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dce_calcs.c | 1073 /*the dispclk required is the maximum for all surfaces of the maximum of the source pixels for first output pixel times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, and the source pixels for last output pixel, times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, plus the active time.*/
1270 /*for cpu p-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration*/
1271 /*for cpu c-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration and recovery*/
1276 /* recovery time > (display bw * blackout duration + (2 * urgent latency + dmif burst time)*dispclk - dmif size )*/
1277 /* / (dispclk - display bw)*/
1364 /*for dram speed/p-state change to be possible for a yclk(pclk) and sclk level there has to be positive margin and the dispclk required has to be*/
1647 /*dispclk*/
1648 /*if dispclk is set to the maximum, ramping is not required. dispclk required without ramping is less than the (…)
[all...] |
| amdgpu_dcn_calc_auto.c | 325 /*maximum dispclk/dppclk support check*/
1184 /*dispclk and dppclk calculation*/
1220 v->dispclk = v->dispclk_without_ramping;
1223 v->dispclk = v->max_dispclk[number_of_states];
1226 v->dispclk = v->dispclk_with_ramping;
1228 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio;
1648 v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk;
1659 v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk);
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| calcs_logger.h | 334 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk: %d", bw_fixed_to_int(data->dispclk));
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| amdgpu_dcn_calcs.c | 483 input.clks_cfg.dispclk_mhz = v->dispclk;
675 * disable optional pipe split by lower dispclk bounding box
1139 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| amdgpu_rn_clk_mgr.c | 267 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
305 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
306 regs_and_bypass->dispclk,
348 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_atombios_crtc.c | 780 u32 dispclk)
801 args.v5.usPixelClock = cpu_to_le16(dispclk);
808 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
2053 /* XXX: DCE5, make sure voltage, dispclk is high enough */
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