| /src/sys/lib/libkern/arch/sh3/ |
| udivsi3.S | 72 #define DIVSTEP rotcl r4; div1 r5, r0
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| udivsi3_i4i.S | 80 #define DIVSTEP rotcl r1; div1 r5, r0
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| sdivsi3.S | 78 #define DIVSTEP rotcl r0; div1 r1, r3
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| sdivsi3_i4i.S | 89 #define DIVSTEP rotcl r0; div1 r1, r3
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| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_sorgf119.c | 129 u32 div1 = sor->asy.link == 3; local
137 nvkm_mask(device, 0x612300 + soff, 0x00000707, (div2 << 8) | div1);
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| /src/sys/dev/i2c/ |
| adm1026.c | 439 uint8_t reg, div1, div2, val; local
448 if (adm1026_read_reg(sc, reg, &div1) != 0) {
452 sc->sc_fandiv[0] = 1 << ADM1026_FAN0_DIV(div1);
453 sc->sc_fandiv[1] = 1 << ADM1026_FAN1_DIV(div1);
454 sc->sc_fandiv[2] = 1 << ADM1026_FAN2_DIV(div1);
455 sc->sc_fandiv[3] = 1 << ADM1026_FAN3_DIV(div1);
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| sht4x.c | 768 uint64_t div1 = 10000; local
810 q = ((v2 * (svalue / d1)) + v1) / div1;
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| sht3x.c | 1291 uint64_t div1 = 10000; local
1304 q = ((v2 * (svalue / d1)) + v1) / div1;
1317 uint64_t div1 = 10000; local
1330 q = ((v2 * (svalue / d1)) + v1) / div1;
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| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_ddi.c | 1458 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; local
1491 div1 = 2;
1494 div1 = 3;
1497 div1 = 5;
1500 div1 = 7;
1521 tmp = div_u64(tmp, 5 * div1 * div2);
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| intel_dpll_mgr.c | 2685 int div1 = div1_vals[i]; local
2688 int dco = div1 * div2 * clock_khz * 5;
2709 switch (div1) {
2711 MISSING_CASE(div1);
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