| /src/sys/arch/arm/s3c2xx0/ |
| s3c2410.c | 208 uint32_t pllcon, divn; local
213 divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN);
221 if (divn & CLKDIVN_HDIVN)
224 if (divn & CLKDIVN_PDIVN)
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| s3c2440.c | 240 uint32_t pllcon, divn, camdivn; local
245 divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN);
256 switch( (divn & CLKDIVN_HDIVN_MASK) >> CLKDIVN_HDIVN_SHIFT )
285 if (divn & CLKDIVN_PDIVN)
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| /src/sys/arch/evbarm/stand/boot2440/ |
| main.c | 410 uint32_t pllcon, divn, camdivn; local
415 divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN);
426 switch( (divn & CLKDIVN_HDIVN_MASK) >> CLKDIVN_HDIVN_SHIFT )
455 if (divn & CLKDIVN_PDIVN)
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| /src/sys/arch/arm/nvidia/ |
| tegra124_car.c | 1025 u_int divm, divn, divp; local
1038 divn = __SHIFTOUT(base, tpll->divn_mask);
1045 rate = (uint64_t)rate_parent * divn;
1068 const u_int divn = rate / rate_parent; local
1085 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN);
1109 const u_int divn = (rate << pldiv) / rate_parent; local
1114 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) |
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| tegra210_car.c | 1147 u_int divm, divn, divp; local
1160 divn = __SHIFTOUT(base, tpll->divn_mask);
1173 rate = (uint64_t)rate_parent * divn;
1196 const u_int divn = rate / rate_parent; local
1213 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN);
1237 const u_int divn = (rate << pldiv) / rate_parent; local
1242 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) |
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| tegra124_cpu.c | 87 u_int divn; member in struct:tegra124_cpufreq_rate
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