| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_compressor.c | 88 status_pos = dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_POSITION));
92 if (status_pos != dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_POSITION))) {
94 value = dm_read_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL));
99 frame_count = dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_FRAME_COUNT));
103 if (frame_count != dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_FRAME_COUNT)))
111 value = dm_read_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL));
127 value = dm_read_reg(cp110->base.ctx, addr);
153 value = dm_read_reg(compressor->ctx, addr);
168 value = dm_read_reg(compressor->ctx, addr);
175 value = dm_read_reg(compressor->ctx, addr)
[all...] |
| amdgpu_dce110_timing_generator_v.c | 90 value = dm_read_reg(tg->ctx,
108 uint32_t value = dm_read_reg(tg->ctx, addr);
128 uint32_t value = dm_read_reg(tg->ctx, addr);
153 value = dm_read_reg(tg->ctx, addr);
166 value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION);
178 value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION);
265 value = dm_read_reg(ctx, addr);
274 value = dm_read_reg(ctx, addr);
283 value = dm_read_reg(ctx, addr);
306 value = dm_read_reg(ctx, addr)
[all...] |
| amdgpu_dce110_mem_input_v.c | 50 value = dm_read_reg(
163 value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE);
376 value = dm_read_reg(
428 value = dm_read_reg(
448 value = dm_read_reg(
482 value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_UPDATE);
613 value = dm_read_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT);
619 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL);
625 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL);
630 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C)
[all...] |
| amdgpu_dce110_timing_generator.c | 105 value = dm_read_reg(tg->ctx, addr);
118 regval = dm_read_reg(tg->ctx, address);
162 uint32_t value = dm_read_reg(tg->ctx, addr);
204 value = dm_read_reg(tg->ctx, addr);
267 regval = dm_read_reg(tg->ctx,
384 v_total_min = dm_read_reg(tg->ctx, addr);
387 v_total_max = dm_read_reg(tg->ctx, addr);
390 v_total_cntl = dm_read_reg(tg->ctx, addr);
489 static_screen_cntl = dm_read_reg(tg->ctx, addr);
522 uint32_t value = dm_read_reg(tg->ctx, addr)
[all...] |
| amdgpu_dce110_opp_regamma_v.c | 44 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);
78 value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);
95 value = dm_read_reg(xfm_dce->base.ctx,
528 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);
|
| amdgpu_dce110_opp_csc_v.c | 119 uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL);
371 uint32_t value = dm_read_reg(ctx, addr);
470 uint32_t value = dm_read_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL);
560 value = dm_read_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL);
|
| amdgpu_dce110_transform_v.c | 285 value = dm_read_reg(xfm_dce->base.ctx, mmSCLV_UPDATE);
309 power_ctl = dm_read_reg(ctx, mmDCFEV_MEM_PWR_CTRL);
317 dm_read_reg(ctx, mmDCFEV_MEM_PWR_STATUS),
516 value = dm_read_reg(xfm_dce->base.ctx, mmLBV_MEMORY_CTRL);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_compressor.c | 307 value = dm_read_reg(cp110->base.ctx, addr);
330 value = dm_read_reg(compressor->ctx, addr);
345 value = dm_read_reg(compressor->ctx, addr);
352 value = dm_read_reg(compressor->ctx, addr);
399 value = dm_read_reg(compressor->ctx, addr);
430 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
454 value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
461 value = dm_read_reg(compressor->ctx, mmFBC_MISC);
463 value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
478 uint32_t value = dm_read_reg(compressor->ctx
[all...] |
| amdgpu_dce112_hw_sequencer.c | 82 value = dm_read_reg(ctx, addr);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/ |
| amdgpu_irq_service.c | 100 uint32_t value = dm_read_reg(irq_service->ctx, addr);
137 uint32_t value = dm_read_reg(irq_service->ctx, addr);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_timing_generator.c | 97 uint32_t value = dm_read_reg(tg->ctx, addr);
135 uint32_t value = dm_read_reg(tg->ctx, addr);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| amdgpu_dc_helper.c | 270 reg_val = dm_read_reg(ctx, addr);
334 uint32_t reg_val = dm_read_reg(ctx, addr);
343 uint32_t reg_val = dm_read_reg(ctx, addr);
354 uint32_t reg_val = dm_read_reg(ctx, addr);
367 uint32_t reg_val = dm_read_reg(ctx, addr);
382 uint32_t reg_val = dm_read_reg(ctx, addr);
399 uint32_t reg_val = dm_read_reg(ctx, addr);
418 uint32_t reg_val = dm_read_reg(ctx, addr);
439 uint32_t reg_val = dm_read_reg(ctx, addr);
461 reg_val = dm_read_reg(ctx, addr)
[all...] |
| dm_services.h | 67 #define dm_read_reg(ctx, address) \ macro
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/ |
| amdgpu_irq_service_dce110.c | 53 uint32_t value = dm_read_reg(irq_service->ctx, addr);
60 value = dm_read_reg(irq_service->ctx, info->enable_reg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/ |
| amdgpu_irq_service_dce120.c | 52 uint32_t value = dm_read_reg(irq_service->ctx, addr);
61 value = dm_read_reg(irq_service->ctx, info->enable_reg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/ |
| amdgpu_irq_service_dce80.c | 52 uint32_t value = dm_read_reg(irq_service->ctx, addr);
61 value = dm_read_reg(irq_service->ctx, info->enable_reg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/ |
| amdgpu_irq_service_dcn10.c | 133 uint32_t value = dm_read_reg(irq_service->ctx, addr);
142 value = dm_read_reg(irq_service->ctx, info->enable_reg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/ |
| amdgpu_irq_service_dcn20.c | 133 uint32_t value = dm_read_reg(irq_service->ctx, addr);
142 value = dm_read_reg(irq_service->ctx, info->enable_reg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/ |
| amdgpu_irq_service_dcn21.c | 134 uint32_t value = dm_read_reg(irq_service->ctx, addr);
143 value = dm_read_reg(irq_service->ctx, info->enable_reg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_hw_sequencer.c | 98 value = dm_read_reg(ctx, addr);
118 value = dm_read_reg(ctx, addr);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_link_encoder.c | 503 uint32_t value = dm_read_reg(ctx, addr);
510 value = dm_read_reg(ctx, addr);
1380 uint32_t value = dm_read_reg(ctx, addr);
1393 uint32_t value = dm_read_reg(ctx, addr);
|
| amdgpu_dce_dmcu.c | 882 psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_link_encoder.c | 272 dm_read_reg(CTX, AUX_REG(reg_name))
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_link_encoder.c | 1346 dm_read_reg(CTX, HPD_REG(reg_name))
1378 dm_read_reg(CTX, AUX_REG(reg_name))
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 42 dm_read_reg(CTX, REG(reg_name))
|
