| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_opp_regamma_v.c | 75 dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value);
104 dm_write_reg(xfm_dce->base.ctx,
118 dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CONTROL, 0);
156 dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL,
167 dm_write_reg(xfm_dce->base.ctx,
178 dm_write_reg(xfm_dce->base.ctx,
195 dm_write_reg(xfm_dce->base.ctx,
227 dm_write_reg(
260 dm_write_reg(xfm_dce->base.ctx,
292 dm_write_reg(xfm_dce->base.ctx
[all...] |
| amdgpu_dce110_opp_csc_v.c | 147 dm_write_reg(ctx, addr, value);
165 dm_write_reg(ctx, addr, value);
183 dm_write_reg(ctx, addr, value);
201 dm_write_reg(ctx, addr, value);
219 dm_write_reg(ctx, addr, value);
237 dm_write_reg(ctx, addr, value);
261 dm_write_reg(ctx, addr, value);
279 dm_write_reg(ctx, addr, value);
297 dm_write_reg(ctx, addr, value);
315 dm_write_reg(ctx, addr, value)
[all...] |
| amdgpu_dce110_timing_generator_v.c | 70 dm_write_reg(tg->ctx,
75 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value);
80 dm_write_reg(tg->ctx,
96 dm_write_reg(tg->ctx,
122 dm_write_reg(tg->ctx, addr, value);
142 dm_write_reg(tg->ctx, addr, value);
271 dm_write_reg(ctx, addr, value);
280 dm_write_reg(ctx, addr, value);
303 dm_write_reg(ctx, addr, value);
325 dm_write_reg(ctx, addr, value)
[all...] |
| amdgpu_dce110_compressor.c | 97 dm_write_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL), value);
114 dm_write_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL), value);
165 dm_write_reg(compressor->ctx, addr, value);
172 dm_write_reg(compressor->ctx, addr, value);
177 dm_write_reg(compressor->ctx, addr, value);
183 dm_write_reg(compressor->ctx, addr, value);
187 dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
190 dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
213 dm_write_reg(compressor->ctx, addr, value);
224 dm_write_reg(compressor->ctx, addr, value)
[all...] |
| amdgpu_dce110_mem_input_v.c | 58 dm_write_reg(
79 dm_write_reg(
93 dm_write_reg(
115 dm_write_reg(
129 dm_write_reg(
165 dm_write_reg(mem_input110->base.ctx,
207 dm_write_reg(
229 dm_write_reg(
260 dm_write_reg(
268 dm_write_reg(
[all...] |
| amdgpu_dce110_transform_v.c | 106 dm_write_reg(ctx, addr, value);
120 dm_write_reg(ctx, addr, value);
136 dm_write_reg(ctx, addr, value);
150 dm_write_reg(ctx, addr, value);
180 dm_write_reg(ctx, mmSCLV_TAP_CONTROL, value);
211 dm_write_reg(ctx, mmSCLV_MODE, value);
220 dm_write_reg(ctx, mmSCLV_CONTROL, value);
271 dm_write_reg(xfm_dce->base.ctx,
275 dm_write_reg(xfm_dce->base.ctx,
287 dm_write_reg(xfm_dce->base.ctx, mmSCLV_UPDATE, value)
[all...] |
| amdgpu_dce110_timing_generator.c | 121 dm_write_reg(tg->ctx, address, regval);
145 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
149 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value);
180 dm_write_reg(tg->ctx, addr, value);
227 dm_write_reg(tg->ctx, addr, value);
230 dm_write_reg(tg->ctx, addr, value);
277 dm_write_reg(tg->ctx,
466 dm_write_reg(tg->ctx, addr, v_total_min);
469 dm_write_reg(tg->ctx, addr, v_total_max);
472 dm_write_reg(tg->ctx, addr, v_total_cntl)
[all...] |
| amdgpu_dce110_hw_sequencer.c | 152 dm_write_reg(ctx, addr, value);
187 dm_write_reg(ctx, addr, value);
236 dm_write_reg(ctx,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_compressor.c | 342 dm_write_reg(compressor->ctx, addr, value);
349 dm_write_reg(compressor->ctx, addr, value);
354 dm_write_reg(compressor->ctx, addr, value);
360 dm_write_reg(compressor->ctx, addr, value);
364 dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
367 dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
405 dm_write_reg(compressor->ctx, addr, value);
414 dm_write_reg(compressor->ctx, addr, value);
416 dm_write_reg(compressor->ctx, addr, value);
432 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data)
[all...] |
| amdgpu_dce112_hw_sequencer.c | 114 dm_write_reg(ctx, addr, value);
146 dm_write_reg(ctx,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/ |
| amdgpu_irq_service.c | 104 dm_write_reg(irq_service->ctx, addr, value);
141 dm_write_reg(irq_service->ctx, addr, value);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_dmcu.c | 251 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
263 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
268 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
316 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
674 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
686 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
691 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
726 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
|
| amdgpu_dce_link_encoder.c | 507 dm_write_reg(ctx, addr, value);
515 dm_write_reg(ctx, addr, value);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_hw_sequencer.c | 115 dm_write_reg(ctx, addr, value);*/
150 dm_write_reg(ctx, addr, value);
185 dm_write_reg(ctx,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_timing_generator.c | 110 dm_write_reg(tg->ctx, addr, value);
187 dm_write_reg(tg->ctx, addr, value);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_hw_sequencer.c | 102 dm_write_reg(ctx,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| amdgpu_dc_helper.c | 272 dm_write_reg(ctx, addr, reg_val);
301 dm_write_reg(ctx, addr, reg_val);
539 dm_write_reg(ctx, addr_index, index);
540 dm_write_reg(ctx, addr_data, data);
555 dm_write_reg(ctx, addr_index, index);
|
| dm_services.h | 72 #define dm_write_reg(ctx, address, value) \ macro
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/ |
| amdgpu_irq_service_dce110.c | 66 dm_write_reg(irq_service->ctx, info->enable_reg, value);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/ |
| amdgpu_irq_service_dce120.c | 69 dm_write_reg(irq_service->ctx, info->enable_reg, value);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/ |
| amdgpu_irq_service_dce80.c | 69 dm_write_reg(irq_service->ctx, info->enable_reg, value);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/ |
| amdgpu_irq_service_dcn10.c | 150 dm_write_reg(irq_service->ctx, info->enable_reg, value);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/ |
| amdgpu_irq_service_dcn20.c | 150 dm_write_reg(irq_service->ctx, info->enable_reg, value);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/ |
| amdgpu_irq_service_dcn21.c | 151 dm_write_reg(irq_service->ctx, info->enable_reg, value);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_link_encoder.c | 275 dm_write_reg(CTX, AUX_REG(reg_name), val)
|
