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    Searched refs:dm_write_reg_soc15 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_timing_generator.c 266 dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_GSL_WINDOW, tg110->offsets.crtc, 0);
429 dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value);
523 dm_write_reg_soc15(
533 dm_write_reg_soc15(
701 dm_write_reg_soc15(tg->ctx,
723 dm_write_reg_soc15(
790 dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL,
951 dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, 0);
990 dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);
1003 dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dm_services.h 171 #define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ macro

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